On Wed, 17 Mar 2010 11:41:50 -0400 Jim Mulder <[email protected]> wrote:
:>> :>> I don't see any obvious Millicode support for the AR address, so I :>query :>> :>- :>> :>> when a PC defined with an ARR is executed, does it cause an :>interrupt :>> :>which :>> :>> then issues IEAARR under the covers? That a FRR would be faster? :>> :> ARR is a software concept, not machine architecture. Nothing :>special :>> :>happens with regard to an ARR when the PC instruction is executed. :>> :> RTM2 processing examines the linkage stack to look for ARRs. :>> Maybe I am looking in the wrong manual, but the POPs does not show me :>where :>> this ARR pointer is saved in either the Entry Table or Linkage Stack :>entry. :> z/OS uses the Entry Parameter in the Entry-Table Entry to point to an :>area of ESQA storage which contains the user parms and the ARR :>information. Would that mean that the latent parameter area is longer, and that I just use the first two words? I still get the same R4, correct? :>> But if I understand you correctly, enabling the ARR as part of a PC :>> instruction is free? :> Yes. Thanks. -- Binyamin Dissen <[email protected]> http://www.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel Should you use the mailblocks package and expect a response from me, you should preauthorize the dissensoftware.com domain. I very rarely bother responding to challenge/response systems, especially those from irresponsible companies. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
