On 4/29/2011 9:35 PM, Barkow, Eileen wrote:
From principles of operation:
Both BRANCH AND LINK and BRANCH AND SAVE have an R1 field. They form a branch
address by means of fields that depend on the instruction. The operations of
the instructions are summarized as follows:
In the 24-bit addressing mode, both instructions place the return address in
bit positions 40-63 of general register R1 and leave bits 0-31 of that register
unchanged. BRANCH AND LINK places the instruction-length code for the
instruction and also the condition code and program mask from the current PSW
in bit positions 32-39 of general register R1. BRANCH AND SAVE places zeros in
those bit positions.
In the 31-bit addressing mode, both instructions place the return address in
bit positions 33-63 and a one in bit position 32 of general register R1, and
they leave bits 0-31 of the register unchanged.
In the 64-bit addressing mode, both instructions place the return address in
bit positions 0-63 of general register R1.
In any addressing mode, both instructions generate the branch address under the
control of the current addressing mode. The instructions place bits 0-63 of the
branch address in bit positions 64-127 of the PSW. In the RR format, both
instructions do not perform branching if the R2 field of the instruction is
zero.
Wait wait...
Are you saying hercules has the instruction correctly, but some other
implementation isn't ?
(Just checked the BALR implementation... it DOES what the z/Arch POP says).
AMODE : Bit mapping
---------------------
24 Bit : [ILC|CC](8)|IA(24) (32 bit reg)
31 Bit : 1(1)|IA(31) (32 bit reg)
64 Bit : IA(64) (64 bit reg)
(in which case my BASR comment was moot !)
--Ivan
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