[email protected] (Timothy Sipples) writes: > That's not really true. For example, there was the IBM Engineering and > Scientific Subroutine Library (ESSL) Vector and Scalar/370 software. That > software provided a library of mathematical functions you could call from > FORTRAN, C, PL/I, APL2, or Assembler programs on MVS or VM. It was also > supported for the languages that ran on AIX/ESA. Program number was > 5688-226, and it was withdrawn from marketing in 2001. VS FORTRAN Version 2 > (not sure which release) also had some automatic vector support of its own. > > The Vector Facility for 3090s was announced on October 1, 1985. > Announcement letter 185-121 is still available on IBM's announcements Web > site (http://www.ibm.com/common/ssi). At the time you could rent your first > Vector Facility for a list price of $30,830 per month and any subsequent > VFs for $19,170 per month. The purchases prices were $370,000 and $230,000, > respectively. All prices are in 1985 dollars, of course. > > Before that there was the IBM 3838 Array Processor which ran (eventually) > the Vector Processing Subsystem (VPSS)/XA. I think the 3838 debuted in 1976 > or 1977. Your VPSS stuff could run on the VFs using (what else) VPSS/VF. > VPSS/XA was IBM Program Number 5665-301. VPS/XA also supported FORTRAN, at > least. > > And before *that* there was the IBM 2938 Array Processor which you attached > to your System/360. > > By the way, you could think of today's zEnterprise BladeCenter Extension > (zBX) as a mainframe vector processor...plus lots of other capabilities.
re: http://www.garlic.com/~lynn/2011h.html#68 IBM Mainframe (1980's) on You tube http://www.garlic.com/~lynn/2011h.html#69 IBM Mainframe (1980's) on You tube http://www.garlic.com/~lynn/2011h.html#72 Vector processors on the 3090 http://www.garlic.com/~lynn/2011h.html#73 Vector processors on the 3090 there were a couple groups in kingston ... one was the E&S center that had a 3090VF (as well as 20 Floating Point Systems boxes) and the group that was supposedly designing an IBM supercomputer ... but was also funding/supporting various other activities ... like the HiPPI I/O interface for 3090 and providing funding for Chen Supercomputer company. long winded thread in a.f.c. from last year http://www.garlic.com/~lynn/2010b.html#71 Happy DEC-10 Day http://www.garlic.com/~lynn/2010b.html#72 Happy DEC-10 Day http://www.garlic.com/~lynn/2010b.html#73 Happy DEC-10 Day http://www.garlic.com/~lynn/2010b.html#74 Happy DEC-10 Day and later thread in comp.arch http://www.garlic.com/~lynn/2010f.html#47 Nonlinear systems and nonlocal supercomputing http://www.garlic.com/~lynn/2010f.html#48 Nonlinear systems and nonlocal supercomputing http://www.garlic.com/~lynn/2010f.html#49 Nonlinear systems and nonlocal supercomputing http://www.garlic.com/~lynn/2010f.html#50 Nonlinear systems and nonlocal supercomputing As mentioned in above, oct91, the senior executive sponsonsoring the supercomputer effort retired and there was lots of review of various projects. then there was an effort to canvas the company to find something for supercomputer (they found the effort I was doing in mid-jan92, and over a couple weeks, it was transferred to Kingston, we were told we couldn't work on anything with than four more processors and it was announced as supercomputer). misc. email from late 91 & early 92 http://www.garlic.com/~lynn/lhwemail.html#medusa This old post describes the ('87) cornell national supercomputer facility with 3090-400 VF and five FPS boxes http://www.garlic.com/~lynn/200c.html#2000c.html#61 TF-1 some followon in this old thread: http://www.garlic.com/~lynn/2000d.html#2 IBM's "ASCI White" and "Big Blue" architecture? http://www.garlic.com/~lynn/2000d.html#3 IBM's "ASCI White" and "Big Blue" architecture? http://www.garlic.com/~lynn/2000d.html#8 IBM's "ASCI White" and "Big Blue" architecture? above references the 1.5gflops peak for 375mhz power3-ii chip is approx. same as the aggregate for IBM Kingston E&S lab in 1985 (with all the FPS boxes) HiPPI was the standards version of Cray 100mbyte/sec parallel (aka half-duplex) channel (standards effort driven out of LANL). 3090 I/O wasn't capable of handle the rate ... so a hack was done in the side of 3090 extended store bus ... with peek/poke semantics; aka basicaly i/o commands & data were read/written to special addresses on the 3090 extended store bus. Later there was serial-HiPPI (with fiber) which then sort of merges with FCS (standards effort driven out of LLNL for 1gbit fiber full-duplex; POK gets involved and there is now FICON flavor of FCS). -- virtualization experience starting Jan1968, online at home since Mar1970 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
