I believe this has been answered before. However, the reason is because of what happens in the manufacturing of the chips.
Some chips yield faster clocking results than the established minimum and maximum. The best of the maximums are set aside and, voila, you have a turbo model. Those below the minimum used to be sold to HDS! (only kidding about that last part...I think) <grin> Bob -----Original Message----- From: IBM Mainframe Discussion List [mailto:[EMAIL PROTECTED] On Behalf Of Pommier, Rex R. Sent: Friday, March 24, 2006 3:40 PM To: [email protected] Subject: Re: z900 "Capacity Models"? I saw that too, from Cheryl's list. But if they don't, IBM's document that I referred to is incorrect. It says that both the 10x and the 1Cx models have a 1.3 nanosecond cycle time and the 2Cx and 21x models have a 1.09 nanosecond cycle time. Maybe IBM did something different in building the blocks or memory interleaving or something to get the additional boost. Ideas, anybody? LEGAL DISCLAIMER The information transmitted is intended solely for the individual or entity to which it is addressed and may contain confidential and/or privileged material. Any review, retransmission, dissemination or other use of or taking action in reliance upon this information by persons or entities other than the intended recipient is prohibited. If you have received this email in error please contact the sender and delete the material from any computer. Seeing Beyond Money is a service mark of SunTrust Banks, Inc. [ST:XCL] ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
