DASDBill2 wrote: > I once wrote a deblocker program to read in 640K tape blocks and break them > up into QSAM-friendly chunks of 32,760 bytes or less. It was an interesting > exercise, made even more so by having to run it on MVS under VM, which caused > a lot of unrepeatable chaining check errors due to the very long channel > program to read in 640K in one I/O request.
cp/67 on 360/67 had to translate ccws from the virtual machine ... and use data-chaining where the virtual machine CCW virtual data address was contiguous ... but the virtual pages from the virtual machine were scattered around memory. moving to 370, IDALs were provided in lieu of data-chaining to break up virtual contiguous areas into non-contiguous pages. part of this is that the standard channel architecture precluded pre-fetching CCWs (they had to be fetched and executed syncronously). on 360, breaking a single ccw into multiple (data-chaining) CCWs introduced additional latencies that could result in timing errors. on 370, non-contiguous areas could be handled with IDALs ... and channel architecture allowed prefetching of IDALs ... supposedly eliminating the timing latencies associated that could happen with data-chaining approach. This issue of channels working with real addresses necessitating CCWs built with virtual address ... to be translated to a shadow set of CCWs with real addresses ... affects all systems operating with virtual memory (which support applications building CCWs with virtual memory addresses ... including the virtual address space area may appear linear ... but the corresponding virtual pages are actually non-contiguous in real memory). The original implementation of os/vs2 was built using standard MVT with virtual address space tables and page interrupt handler hacked into the side (for os/vs2 svs ... precursor to os/vs2 mvs ... since shorten to just mvs). It also borrowed CCWTRANS from cp/67 to translate the application CCWs (that had been built with virtual addresses) into "real" CCWs that were built with real addresses for real execution. This version of CCWTRANS had support for IDALs for running on 370s. Typically, once MVS had shadowed the application CCWs ... creating the shadow CCWs with IDALs giving the non-contiguous page addresses ... then any VM translation of the MVS translated CCWs was strictly one-for-one replacement ... an exact copy of the MVS set of translated CCWs ... which only differed in the real, real address spacified. all the virtual machine stuff and cp67 had been developed by the science cneter http://www.garlic.com/~lynn/subtopic.html#545tech there was a joint project between cambridge and endicott to simulate virtual 370s under cp67 running on real 360/67 (for one thing the 370 virtual memory tables had somewhat different hardware definition, the control register definitions were somewhat different, there some different instructions, etc). the base production system at cambridge was referred to as cp67l. the modifications to cp67 to provide 370 virtual machines (as an alternative option to providing 360 virtual machines) was referred to as cp67h. Then further modifications were made to cp67 for the kernel to run on real 370 (using 370 hardware definitions instead of 360 hardware definitions). This cp67 kernel that ran "on" 370 hardware was referred to as cp67i. cp67i was running regularly in production virtual machine a year prior to the first engineering 370 model with virtual memory hardware became available (in fact, cp67i was used as a validation test for the machine when it first became operational). cms multi-level source update management was developed in support of cp67l/cp67h/cp67i set of updates. also, the cp67h system ... which could run on a real 360/67, providing virtual 370 machines ... was actually typically run in a virtual 360/67 virtual machine ... under cp67l on the cambridge 360/67. This was in large part because of security concerns since the cambridge system provided some amount of generalized time-sharing to various univ. people in the cambridge area (mit, harvard, bu, etc). If cp67h was hosted as the base timesharing service ... there were all sorts of people that might trip over the unannounced 370 virtual memory operation. about the time some 370s (145) processors became available internally (still long before announcement) a couple engineers came out from san jose and added the device support for 3330s and 2505s to the cp67i system (including multi-exposure support, set sector in support of rps). also idal support was crafted into CCWTRANs. part of the issue was that the channels on real 360/67s were a lot faster and had lot lower latency ... so there were much fewer instances where breaking a single CCW into multiple data-chained CCWs resulted in overruns. However, 145 channel processing was much slower and required (prefetch'able) IDALs to avoid a lot of the overrun situations. a few past posts mentioning cp67l, cp67h, and cp67i activity: http://www.garlic.com/~lynn/2002h.html#50 crossreferenced program code listings http://www.garlic.com/~lynn/2002j.html#0 HONE was .. Hercules and System/390 - do we need it? http://www.garlic.com/~lynn/2004b.html#31 determining memory size http://www.garlic.com/~lynn/2004d.html#74 DASD Architecture of the future http://www.garlic.com/~lynn/2004p.html#50 IBM 3614 and 3624 ATM's http://www.garlic.com/~lynn/2005c.html#59 intel's Vanderpool and virtualization in general http://www.garlic.com/~lynn/2005d.html#58 Virtual Machine Hardware http://www.garlic.com/~lynn/2005g.html#17 DOS/360: Forty years http://www.garlic.com/~lynn/2005h.html#18 Exceptions at basic block boundaries http://www.garlic.com/~lynn/2005i.html#39 Behavior in undefined areas? http://www.garlic.com/~lynn/2005j.html#50 virtual 360/67 support in cp67 http://www.garlic.com/~lynn/2005p.html#27 What ever happened to Tandem and NonStop OS ? http://www.garlic.com/~lynn/2005p.html#45 HASP/ASP JES/JES2/JES3 http://www.garlic.com/~lynn/2006.html#38 Is VIO mandatory? http://www.garlic.com/~lynn/2006e.html#7 About TLB in lower-level caches misc. past posts mentioning cp/67 CCWTRAN http://www.garlic.com/~lynn/2000.html#68 Mainframe operating systems http://www.garlic.com/~lynn/2000c.html#34 What level of computer is needed for a computer to Love? http://www.garlic.com/~lynn/2001b.html#18 Linux IA-64 interrupts [was Re: Itanium benchmarks ...] http://www.garlic.com/~lynn/2001i.html#37 IBM OS Timeline? http://www.garlic.com/~lynn/2001i.html#38 IBM OS Timeline? http://www.garlic.com/~lynn/2001l.html#36 History http://www.garlic.com/~lynn/2002c.html#39 VAX, M68K complex instructions (was Re: Did Intel Bite Off More Than It Can Chew?) http://www.garlic.com/~lynn/2002g.html#61 GE 625/635 Reference + Smart Hardware http://www.garlic.com/~lynn/2002j.html#70 hone acronym (cross post) http://www.garlic.com/~lynn/2002l.html#65 The problem with installable operating systems http://www.garlic.com/~lynn/2002l.html#67 The problem with installable operating systems http://www.garlic.com/~lynn/2002n.html#62 PLX http://www.garlic.com/~lynn/2003b.html#0 Disk drives as commodities. Was Re: Yamhill http://www.garlic.com/~lynn/2003g.html#13 Page Table - per OS/Process http://www.garlic.com/~lynn/2003k.html#27 Microkernels are not "all or nothing". Re: Multics Concepts For http://www.garlic.com/~lynn/2004.html#18 virtual-machine theory http://www.garlic.com/~lynn/2004c.html#59 real multi-tasking, multi-programming http://www.garlic.com/~lynn/2004d.html#0 IBM 360 memory http://www.garlic.com/~lynn/2004g.html#50 Chained I/O's http://www.garlic.com/~lynn/2004m.html#16 computer industry scenairo before the invention of the PC? http://www.garlic.com/~lynn/2004n.html#26 PCIe as a chip-to-chip interconnect http://www.garlic.com/~lynn/2004n.html#54 CKD Disks? http://www.garlic.com/~lynn/2004o.html#57 Integer types for 128-bit addressing http://www.garlic.com/~lynn/2005b.html#23 360 DIAGNOSE http://www.garlic.com/~lynn/2005b.html#49 The mid-seventies SHARE survey http://www.garlic.com/~lynn/2005b.html#50 [Lit.] Buffer overruns http://www.garlic.com/~lynn/2005f.html#45 Moving assembler programs above the line http://www.garlic.com/~lynn/2005f.html#47 Moving assembler programs above the line http://www.garlic.com/~lynn/2005p.html#18 address space http://www.garlic.com/~lynn/2005q.html#41 Instruction Set Enhancement Idea http://www.garlic.com/~lynn/2005s.html#25 MVCIN instruction http://www.garlic.com/~lynn/2005t.html#7 2nd level install - duplicate volsers http://www.garlic.com/~lynn/2006.html#31 Is VIO mandatory? http://www.garlic.com/~lynn/2006.html#38 Is VIO mandatory? http://www.garlic.com/~lynn/2006b.html#25 Multiple address spaces ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
