The ARCH option of the z/OS Enterprise PL/I Compiler supports NOT just four
but six levels, unsurprisingly since the code-generation phases of the two
compilers (C and PL/I) are shared.
The text of the discussion of ARCH in the current V3R5 Enterprise PL/I
Compiler (taken from the Programming Guiide) is:
| ARCH
| The ARCH option specifies the architecture for which the executable
programfs instructions are
| to be generated. It allows the optimizer to take advantage of specific
hardware instruction sets.
| A subparameter specifies the group to which a model number belongs. 2
ARCH ( n )
| The current values that may be specified for the ARCH level are:
|
| 0 Produces code that is executable on all models.
|
| 1 Produces code that executes only on the following and follow-on models:
9021-520, 9021-640, | 9021-660, 9021-740, 9021-820, 9021-860, and 9021-900
9021-xx1 and 9021-xx2 9672-Rx1,
| 9672-Rx2(G1), 9672-Exx, and 9672-Pxx
|
| 2 Produces code that executes only on the following and | follow-on
models: 9672-Rx3(G2),
| 9672-Rx4(G3), 9672-Rx5(G4), and 2003Specifically, these ARCH(2) machines
and their follow-ons
| include the Branch Relative instruction set (Branch Relative | and Save
- BRAS), and the Halfword | Immediate instruction set (for example, Add
Halfword Immediate - AHI).
|
| 3 Produces code that executes only on the following and follow-on models:
9672-xx6 (G5) and
| 9672-xx7 (G6)Specifically, these ARCH(3) machines and their follow-ons
include a set of facilities
| for IEEE floating-point representation, as well as 12 additional
floating-point registers and some
| new floating-point support instructions. ARCH(3) (or higher) is required
for execution of a
| program that uses IEEE floating-point.
|
| 4 Produces code that uses instructions available on model 2064-100
(z/900) in ESA/390 mode..
| Specifically, these ARCH(4) machines support the LALR instruction as well
as the ALCR and SLBR
| instructions which are useful in 8-byte integer arithmetic.
|
| 5 Produces code that uses instructions available on model 2064-100
(z/900) in z/Architecture
| mode. Specifically, these ARCH(5) machines and their follow-ons include
instructions such as NILL,
| NILH, OILL, OILH, LLILL and LLILH.
|
| 6 Produces code that uses instructions available on the 2084-xxx models
in z/Architecture mode. | Specifically, the compiler on these ARCH(6)
machines and their follow-ons may exploit the long-
| displacement instruction set. The long-displacement facility provides a
20-bit signed displacement | field in 69 previously existing instructions
(by using a previously unused byte in the instructions)
| and 44 new instructions. A 20-bit signed displacement allows relative
addressing of up to 524,287 | bytes beyond the location designated by a
base register or base and index register pair and up
| to 524,288 bytes before that location. The enhanced previously existing
instructions generally are | ones that handle 64-bit binary integers. The
new instructions generally are new versions of
| instructions for 32-bit binary integers. The new instructions also
include v A LOAD BYTE
| instruction that sign-extends a byte from storage to form a 32-bit or
64-bit result in a general
| register v New floating-point LOAD and STORE instructions The
long-displacement facility provides | register-constraint relief by
reducing the need for base registers, code size reduction by allowing |
fewer instructions to be used, and additional improved performance through
removal of possible
| address-generation interlocks. If you specify an ARCH value less than 2,
the compiler will reset it
| to 2.
| Note: The x in the model numbers above (such as 9672-Rx4 is a
wildcard and
| stands for any | alphanumeric machine of that type, such as
9627-RA4).Note: Code that is
| compiled at ARCH(n) runs on machines in the ARCH(m) group if and only if
m >= n.
|
The list you seek is implicit in this text. With very little effort you can
extract it.
John Gilmore
Ashland, MA 01721-1817
USA
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