On Thu, 28 Sep 2006 10:38:18 -0400, Gabriel Tully wrote: >I heard it off of a power point slide explaining virtual storage, it >was 'homework': funny I know. I am familiar with segment sizes and >tables and I'm not confusing the two, however perhaps the power point >is. I think this was in reference to how some processors (MIPS) >support multiple page sizes (R4000-style TLB [translation Lookaside >Buffer]) and that zSeries was considering something similar. Now, >that may just be just through the magic of translation and the actual >frame size is constant. I don't know and actually am out of my depth. > But, I still would love to hear your comments. Also, I am certainly >not professing any of this presentation to be accurate and appreciate >the reality checks. Have the presenter review ancient history in the S/360 line -- the 360 line generally supported differing page sizes (2K and 4K) and the 360/67 supported 2K, 4K and even 1M page sizes. (I don't recall whether any SCP shipped that dealt with 1M page sizes, especially in the VERY expensive storage era of the S360 line though. That could be why the idea lurked for lo these many years.) For zSeries to do it you would either be looking at creative use of MIDAW to read/write the 1M pages from/to existing DASD (with less-then-ideal performance) or you would be looking at new DASD (or son-of-DASD maybe). Perhaps it would be a good excuse to resurrect expanded storage (ESTORE) with an also-resurrected Asynchronous Page Mover (of 1M)? I wouldn't forsee the use of 1M pages below the bar for the fragmentation reasons previously mentioned. But above the bar it would make far more sense to have a larger page size (maybe not 1M but 4K is micromanagement). (I wonder if it would cause any TLB/ALB issues?) -- Tom Schmidt Madison, WI (Nope, no inside info here, just speculation based somewhat on history)
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