The following message is a courtesy copy of an article that has been posted to bit.listserv.ibm-main,alt.folklore.computers as well.
[EMAIL PROTECTED] (Shmuel Metz , Seymour J.) writes: > The were also assists for OS/VS1 and MVS/SE, to say nothing of the > infamous ECPS:VSE. re: http://www.garlic.com/~lynn/2007k.html#67 Non-Standard Mainframe Language? http://www.garlic.com/~lynn/2007k.html#70 Non-Standard Mainframe Language? http://www.garlic.com/~lynn/2007k.html#73 Non-Standard Mainframe Language? the 145/148 ... for lots of typical kernel instruction paths ... there was approximately a one-for-one byte translation from 370 into microcode. 145 allowed for scavanging part of processor memory for microcode. that was changed in 148 ... and after the OS/VS1 microcode assist was done for 148 ... there was only 6kbytes left in dedicated 148 microcode storage for VM370 ECPS. This somewhat contributed to us doing a significantly better job of choosing the highest used vm370 instruction paths (vis-a-vis the vs1 effort) for dropping into microcode. basically all the instruction paths thru the vm370 kernel were carefully profiled and then ranked as per use ... and then the top 6k bytes were chosen for migration to 148 m'code ... refs: http://www.garlic.com/~lynn/94.html#21 370 ECPS VM microcode assist http://www.garlic.com/~lynn/94.html#27 370 ECPS VM microcode assist http://www.garlic.com/~lynn/94.html#28 370 ECPS VM microcode assist MVS/SE microcode assist would have been much more problamatical since it was applied to the high-end horizontal m'code machines ... where there was already nearly one-for-one between 370 execution and microcode execution; it wouldn't have been possibly to pick up the 10:1 improvement that you found in the low & mid-ranged microcoded machines (and in some cases, trying to do straight-forward one-for-one movement of blocks of 370 instructions to horizontal microcode, would actually increase processing time). The place where the vm370 virtual machine microcode assists worked across the whole machine line ... was being able to eliminate the priv. op interrupts into the vm370 kernel ... that 370 supervisor state instruction emulation, when running in special "virtual machine" problem state ... executed the instructions directly. This wasn't a one-for-one movement of kernel instructions to microcode instruction ... this was the total elimination of the interrupt processing, context switch, and a bunch of other kernel overhead stuff. This was further demonstrated when Amdahl implemented hypervisor in their "macrocode" ... a sort of 370 instruction set running in special hardware mode. The response was PR/SM on the 3090 (which was a much more difficult undertaking since it was native horizontal microcode programming). ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
