> Binyamin Dissen wrote: > > A SAM** should not require extra cycles and should not cause problems > in the predictive execution.
I have to disagree. I would expect that a change in the addressing mode would force a selective purge of the predictive execution cache. For example, would a SAMxx instruction have any effect on a subsequent LR (18xx) instruction. No. So the predictive execution cache should be unaffected, at least is far as this instruction is concerned. However, how about a subsequent ST (50xx) instruction? Yes, it would absolutely have an impact upon the execution of that instruction, and the predictive execution cache from that instruction forward would likely have to be discarded. I cannot imagine that IBM would be maintaining parallel predictive execution cache entries for all 24-bit, 31-bit, and 64-bit combinatorial possibilities. Lacking any documentation or statement from IBM to the contrary, it is my belief that a change in addressing mode, whether as a consequence of a SAMxx instruction, a BASSM or BSM instruction, or any other mechanism, is an expensive operation, and effectively shuts down the predictive execution capabilities of the processor. John P Baker ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
