On Mon, 10 Sep 2007 14:51:21 -0600, Howard Brazee wrote:
>
>>In the real world, however, clock signals are an extremely effective
>>way of maintaining stability in a digital system, as the analog world
>>and human engineering flaws creep in. A few firms tried making
>>asynchronous designs, perhaps the best known were DECs PDP-6 and KA-10
>>processors, but they learned that noise, uneven speeds of the logic
>>circuits, and race conditions make design very difficult - and
>>servicing a sick machine even worse.
>
>Weren't Crays built with real race logic?
>
>But they have been superseded by technology that finds more value with
>stability.
>
("Race" is such a pejorative word, even in this nonanthropological
sense; use "asynchronous" instead.)
Doesn't the clock logic add whatever stability by making the clock
the slowest element in the system, so the clock loses all races,
then pacing everything else by that? The clock can't make switches
change state any faster than they would in its absence.
The PDP-6 timing diagram contained intriguing instructions similar to:
If the operand is in expanded memory, add 3 nsec for each foot
of cable between the main chassis and the expansion chassis.
(Yes, expanded memory went in a separate chassis!)
-- gil
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