Much of what I was talking about is described here:
http://www.research.ibm.com/journal/rd/446/webb.html
although even this paper is somewhat "dated" by now. My understanding is that
the z9
class microprocessors have a much deeper (longer) pipeline, and the logic that
looks at
instructions very "early" doesn't distinguish "BCTR Rx,0" as a special case,
only that
BCTR, in general, is not in an instruction "class" that can potentially be
executed
immediately (out of order), at least not in the very early pipeline stages. An
"AHI
Rx,-1" on the other hand, is more readily identified as a good candidate, and
thus
stands a better chance of being executed for "free" (simultaneously with one or
more
other instructions).
At 05:36 PM 12/13/2007, Phil Payne wrote:
>> .. BCTR Rx,0 ..
>
>I've had conversations with processor designers at both Amdahl and IBM. The
>general idea is
>that a BCTR that cannot be taken (target register = 0) is recognized as a
>special form of BCTR
>and has been, in fact, since the 360/85.
>
>And a BCTR or BCT with a non-zero target is always assumed taken, although
>with modern
>pipelines it doesn't matter because multiple paths are followed. Exactly how
>many is a
>commercial secret.
>
>These guys get up to stunts it's hard to believe. In-flight register renaming
>has been with
>us for three decades or so.
>
>The last time I hand-coded and tuned a loop for an IBM mainframe was a
>Fibonacci-based parts
>lookup for Ford in about 1974.
[...snip...]
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