IBM Mainframe Discussion List <[email protected]> wrote on 02/04/2008 04:06:40 PM:
> I'm not sure of the mechanism. I'm almost certain the Lynn Wheeler > knows, however. Perhaps he will answer. Whatever the mechanism is, I'm > fairly certain that the z/OS system is unaware, except for timing issues > and performance degradation due to cache and TLB and ALB purges. > > Tom Harper > IMS Utilities Development Team > Neon Enterprise Software > Sugar Land, TX > > -----Original Message----- > From: IBM Mainframe Discussion List [mailto:[EMAIL PROTECTED] On > Behalf Of David Day > Sent: Monday, February 04, 2008 3:00 PM > To: [email protected] > Subject: Re: CPU time differences for the same job > > snip > > and can occur for other LPARs when the > hyper-visor interrupts the processor to dispatch another LPAR. > > snip > > Tom, > What interrupt does the executing TCB/SRB experience when the above > ocurrs? Just curios as to the mechanism used to switch a processor from > one > LAPR to another? > > --Dave Day The currently dispatched logical processor could drop out of SIE due to a host timer interrupt (used by LPAR for time slicing the logical processors), a host I/O interrupt (for example, if a guest I/O completed and there was no enabled logical processor for that guest zone currently dispatched on a physical processor), a host SIGP (could be used by LPAR to preempt a logical processor in order to dispatch higher priority logical processor). The architecture does not provide any mechanism for the guest running in an LPAR zone to be aware of when its logical processors become dispatched and undispatched. You can sometimes indirectly observe some evidence of this activity by looking at SYSTRACE under IPCS in a dump. Starting with z/OS 1.7, the far righthand column provides the physical processor address on which trace trace entry was made. So you might see a particular logical processor (whose address is in the lefthand column) having entries with different physical processor addresses in the righthand column. A time difference between two successive entries for the same logical processor which is considerably larger than you would have otherwise expected might also be due to the logical processor being undispatched and redispatched. Jim Mulder z/OS System Test IBM Corp. Poughkeepsie, NY ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
