Found where I read it (I did not believe it).  I had already heard in
other discussions/presentations on the z10 that they were indeed CISC
chips.  Probably someone assuming z6/Power 6 technology with RISC. 

Another 'The Register' article titled 'IBM chills mainframe New Coke'

http://www.theregister.co.uk/2008/10/21/new_ibm_entry_mainframe/

The article states
'The z10 BC is a cut-down version of the existing z10 Enterprise Class
machine, which launched in March 2008 using Big Blue's quad-core z6 CISC
mainframe processor.' and continues to mention CISC.

One of the comments from readers was 

CISC processors  
By Magellan Posted Tuesday 21st October 2008 22:28 GMT

Mainframes have not used CISC processors in years. They execute CISC
code, but on RISC processors using hardware CISC decoder which converts
the CISC operations to RISC operations. This is exactly what AMD and
Intel have done for years on x86, ever since AMD's K5 and Intel's P6.

I recall reading somewhere there was significant similarity between one
of the IBM mainframe RISC processor cores from the early 2000s and IBM's
in-order RISC RS64 processor core from the late 1990s.
 

-----Original Message-----
John Eells


Ken Porowski wrote:
<snip>
>I heard someone make the 
> comment that even the z10 (and possibly earlier) were RISC with CISC 
> in the milli-micro-etc. code?
<snip>

I have _no_ idea where these rumors come from!

668 of the 894 instructions on the z10 EC (about 75%) are implemented
entirely in hardware.  I don't know about anyone else, but I would not
exactly call 668 hardware instructions "RISC."

For more than you probably want to know, see:

http://www.ibm.com/systems/resources/systems_z_news_announcement_pdf_ZSO
03018.pdf
http://www.redbooks.ibm.com/redpieces/pdfs/sg247515.pdf

--
John Eells
z/OS Technical Marketing
IBM Poughkeepsie
[EMAIL PROTECTED]

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