On 8/16/2012 6:45 AM, zMan wrote:
I suspect Ed was pointing out that the content of the padding byte can affect the result of an MVCL -- that is, the resulting *data*.
I was talking about using the 'cache bypass' capability of MVCL (also MVPG). Dragging large amounts of memory around from one place to another through L1 cache is expensive and also has the side effect of flushing other lines that probably need to be immediately brought back in after the MVCL completes. Of course, the source and target memory addresses must be aligned just right to take advantage of cache bypass. But, if you're moving (for example) 4K pages on a 4K boundary you should see measurable performance differences. If your addresses are unaligned, then there is no difference.
-- Edward E Jaffe Chief Technology Officer Phoenix Software International, Inc 831 Parkview Drive North El Segundo, CA 90245 310-338-0400 x318 [email protected] http://www.phoenixsoftware.com/ ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
