>the PSW would be in STCBPPSW 

Actually, no. STCBPPSW has nothing to do with that, as the comment on that 
field indicates.

This relates to why the PSW is in one RB and the regs are saved in 
another.
You always have a top (most current) RB.  That is where the PSW is saved. 
The external FLIH and I/O FLIH save regs in the TCB. The SVC FLIH saves 
regs in the TCB but will move them to a previous RB when it is obtaining 
an SVRB; it saves the PSW in the new (or existing) top RB. Undispatch 
processing doesn't in and of itself save the PSW (it is saved by the 
processing that chooses to, or chooses not to, initiate undispatch 
processing). The PSW is saved in the the top RB. And it is used from there 
on redispatch.

>What I am doing is canceling the address space with CALLRTM. 
I surely hope you are not doing that. It is unacceptable to use CALLRTM 
yourself to cancel. That is a system-only function. You can use CALLRTM 
TYPE=ABTERM to cause a task to be abterm'd with your own completion code 
(and can choose to indicate "no retry") and if that task is the job step 
program task and if it does terminate, in so doing it will cause the job 
to terminate. It will not cause the address space to terminate if this is 
a job running within an initiator.

>Before that a install a RESMGR exit
I hope you mean that you are using the RESMGR macro to define a resource 
manager. Given what you are writing, you likely want a task RESMGR for one 
specific task - the jobstep program task.

>Is there anyway from a RESMGR exit
>To determine where execution was taking place

If you are talking about an address space RESMGR, no, because the private 
storage of the address space is gone before that runs. f you are talking 
about a task RESMGR, of course. Since it can be  viewed in a dump, you can 
view it while active.  You have access to the tasks and RBs.  With 
appropriate serialization you can scan those queues, although depending on 
what you are doing they might or might not be programming interfaces.

Peter  Relson
z/OS Core Technology Design

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