On Thu, 29 Nov 2012 08:07:13 -0500, John P. Baker wrote:
>According to the z/Architecture Principles of Operation, SA22-7832-09, page >5-9, all 64 bits of the index register are used. Correct. And on the next page, <quote> In forming the intermediate sum, the base address and index are treated as 64-bit binary integers. A 12-bit displacement is treated as a 12-bit unsigned binary integer, and 52 zero bits are appended on the left. A 20-bit displacement is treated as a 20-bit signed binary integer, and 44 bits equal to the sign bit are appended on the left. The three are added as 64-bit binary numbers, ignoring overflow. The sum is always 64 bits long and is used as an intermediate value to form the generated address. </quote> > >My interpretation is that it is not the AMODE, but the architectural mode >that affects the interpretation of the index register. The AMODE determines how many bits of the 64-bit result of the address arithmetic. The address used is a 64-bit address with the high 33 bits set to zero in 31-bit more or the high 40 bits set to zero in 24-bit mode. >On a z/Architecture-capable machine, in ESA mode, bits 0-31 of the index >register are ignored, and bits 32-63 are used. Maybe, but if the POO says that, I don't see it. It seems to me that additional complexity would be required to implement that, and that there would be no benefit. -- Tom Marchant ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
