On Sun, 24 Oct 2021 at 12:11, Paul Gilmartin <[email protected]> wrote:
> What I believe most important is to clarify the distinction between address > generation and storage access. It's easy to overlook this distinction > because 99+% of instructions performing address generation result > immediately in a storage access. (Are the only exceptions LA(Y)?) There is the relative LA instruction LARL, and though the address generation is not base-displacement, it is still covered by the same rules. A handful of instructions perform base/displacement type address calculation but then don't use the result as an address. The most obvious are the shift instructions (e.g. SLL) but there are others both ordinary (e.g. RLL, PC) and privileged (e.g. LASP, SIGP). I believe this is "address generation" as contemplated by the rules in Chapters 3 and 5, because generally these instructions say something like "The second-operand address is not used to address data; its rightmost six bits indicate the number of bit positions to be shifted. The remainder of the address is ignored." There are other instructions that do in a sense use the result as an address but then never read from or write to that address. Most - maybe all - of these are privileged, e.g. LRA and friends. > All RX instructions perform address generation identically, using base. > displacement, and index. Wraparound may occur twice. > > All RS and SS (twice) instructions perform address generation > identically, using base(s) and displacement(s). Wraparound may > occur on each address generated. > > RR instructions such as branches perform address generation by > wraparound of the R2 operand value. > > Omissions? Exceptions? Model dependencies? There certainly shouldn't be model dependencies for this kind of thing, and nothing I can see in the book suggests there are. > No exceptions are recognized during address generation. True for address generation as part of operand address calculation during instruction execution, and for a few other things. Not true for certain other operations that perform address generation. There is a chart 3-3 of all this in Chapter 3 of the POO. Apparent conflicts between Chapters 3 and 5 can, I think, be resolved by noting that Chapter 3's title is Storage, while Chapter 5's is "Program Execution". Tony H. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
