I would not expect the SLIP WAIT to change primary and secondary. You can verify that by displaying CR 3 and 4 for the CPU of interest and comparing it to the CR 3-4 in the IEE844W message.
Jim Mulder -----Original Message----- From: IBM Mainframe Discussion List <[email protected]> On Behalf Of Paul Schuster Sent: Friday, May 20, 2022 2:45 PM To: [email protected] Subject: Question about z/os and VM ADJUNCT I code an IF SLIP with ACTION=WAIT. When it hits, I get the IEE844W message. I start the adjunct, and I want to display the storage at the locations pointed to by the registers. I use the command CPU 0 CMD DISPLAY PRI regval.100 This works for a register that points to common storage, but for a register value that points to private storage I get CPU 0 CMD DISPLAY PRI 7F7FA2E8.100 00: V00000000 00000000 0E R00000000 00: V7F7FA2E8 to 7F7FA3E7 non-addressable storage - page translation exception (At the time the SLIP hit, the register value is valid.) Is there something else I need to specify on the DISPLAY command to get the register value correctly translated to the VM third level storage? Or does the ACTION=WAIT destroy the capability of doing a translation? Thank you. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
