One thought: Look for the value in the SDWABEA field. This is the "Breaking Event Address" >From the POPs: Breaking-Event-Address Register When the PER-3 facility is installed, each CPU has a 64-bit register called the breaking-event-address register. Each time execution of an instruction other than TRANSACTION ABORT replaces the instruction address in the PSW by any means other than sequential instruction execution, the instruction address used to fetch that instruction is placed in the breaking-event-address register.
This is the last address that caused a branch that caused the 0C1. Mike Stayton z/OS Communications Server m...@us.ibm.com ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
