On Mon, 24 Jun 2024 at 17:22, Binyamin Dissen < [email protected]> wrote:
>From the doc it would appear that the ZAD trap would hit even if the > instruction has both index and base register zero specified, such as > > L Rx,PSAAOLD(0,0) > > Am I understanding correctly? > I don't think so. "When the PER zero-address-detection facility is installed, a zero-address-detection event occurs whenever a CPU makes a storage access using an effective operand address formed from a general reg- ister, or subfield of a general register, containing zero. However, during execution of an RX-, RXE-, RXF-, RXY-, or VRX-format instruction, the event occurs only if the CPU makes a storage access using an effective operand address formed under one of the following conditions: 1. The base register number is zero, the index reg- ister number is nonzero, and the index register contains zero. 2. The index register number is zero, the base reg- ister number is nonzero, and the base register contains zero. 3. When both the base register number and the index register number are nonzero, it is unpre- dictable which one of the following conditions causes the event: (a) The base register contains zero. (b) The sum of the contents of the base register and the index register is zero." Tony H. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
