A mea culpa from me since I started this thread: POST with the ASCB parameter 
indeed works.  ASCB requires, as documented, the address of the ASCB.  And the 
parameter supports RX (LA instruction) or register specification (LR) to 
accomplish this.  By using the RX specification (LA), what I was providing was 
the address of the address of the ASCB, rather than the address of the ASCB 
itself, thus the S602 Abend.  And I claimed on September 4 that RX had no use: 
"I don't see how LA of anything would work, yet the macro supports it."   Well, 
RX works, and can be used when the ASCB is within, for example, the caller's 
own addressability.  What I had was already the address of the ASCB in the 
target address space, not the POSTer's address space.  So, the register 
notation LR was required in my case, but the RX (LA) specification is helpful 
for other ASCBs.

So, my apologies, IBM documentation!
Richard Zierdt

________________________________
From: IBM Mainframe Discussion List <[email protected]> on behalf of 
Peter Relson <[email protected]>
Sent: Friday, September 6, 2024 10:07 AM
To: [email protected] <[email protected]>
Subject: Re: POSTing a WAIT in another Address Space; POST ASCB= parameter; 
S602 Abend

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Binyamin wrote:
<snip>
The code attempting the CS needs addressability. Common is not required. Quite
often server PC code has its  post to the server via the CS technique with the
ECB available via an ALET..
</snip>

You're right of course that addressability is the requirement, not common 
storage.

Regarding the client's having an ALET to access storage in the server address 
space: that is certainly possible. I don't know how "common" that is. You could 
be right that it is "quite often".

Peter Relson
z/OS Core Technology Design


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