Hi Johnny, I would not call it two different types of abends.
What the CPU does when an interruption occurs is described in the Principles of Operation manual, chapter 6. The difference in behaviour that you described is caused by the CPU taking different actions when the interrupt occurs. IBM labels these different actions as "Nullified", "Suppressed", "Completed", "Terminated", or "Unaffected". See figure 6-1 for a complete overview. Kind regards, Abe Kornelis ========== On 03/05/2025 05:02, Johnny Luo wrote: > Hi, > > When you execute a "br 14" and r14 contains an invalid address, "br 14" > will be successfully executed (and will be recorded in BEAR) and the > content of r14 will be loaded into PSW. Then an exception will occur while > fetching the next instruction. > > So in my understanding, an ocx could occur at fetch&decode stage as well > as the execution stage. In the former the psw points to the failing > instruction. In the latter the psw point to the next instruction, so IlC > should be used to get the address of the failing instruction. > > Is there something wrong with my above thoughts? > > Thanks. > > Best Regards, > Johnny Luo > > ---------------------------------------------------------------------- > For IBM-MAIN subscribe / signoff / archive access instructions, > send email to [email protected] with the message: INFO IBM-MAIN ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
