So that long displacement instructions are guaranteed to get a S0C4 as well if
the base register is not initialized properly.
On 6/27/2013 8:51 AM, Ed Jaffe wrote:
Why?
On 6/27/2013 8:45 AM, Jim Phoenix wrote:
On 6/27/2013 8:39 AM, Ed Jaffe wrote:
On 6/27/2013 8:25 AM, Paul Gilmartin wrote:
This thread appears to have drifted from a discussion of 7FFFF000
to a discussion of PSA. But a search of z/OZ publibz for the former
finds a few tantalizing references such as:
...
152 (98) ADDRESS 4 OUCBWORKQTOKEN
Server Environment
Address Space Queue
Entry pointer or
7FFFF000
... but no definitive statement that that page is forever excluded,
nor whether it's a hardware or software feature, and of course no
mention of other operating systems.
Is there any such restricted address in AMODE 24?
This was discussed in 2007 on IBM-MAIN.
MVS has guaranteed the 4K "hole" at 7FFFF000 since MVS/XA and will do so in
the future. IBM code depends upon it. There is no equivalent for 24-bit mode.
If it doesn't also protect against long displacement instructions, then it
probably should.
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