[email protected] (Jon Perryman) writes: > Comparing MIPS (or BIPS) for different platforms is useless where > instruction sets are so diverse. While you say the E5-2600 is 10.5 > times the BIPS of the z196, the reality is they are probably close to > the same workload. Consider MVC versus MOV instructions. MVC can move > 256 bytes versus 8 bytes for MOV. On the intel, 128 instructions are > executed for a single MVC (a loop that increments a counter, if count > not reached then loop (4 instructions). 256 bytes / 8 bytes * 4 > instructions = 128 instructions needed for the single MVC > instruction. Your 10.5 number now becomes 0.08. Neither of these > numbers comes close to reflecting a true comparison.
re: http://www.garlic.com/~lynn/2013l.html#50 Mainframe on Cloud http://www.garlic.com/~lynn/2013l.html#51 Mainframe on Cloud dhrystone MIPS http://en.wikipedia.org/wiki/Instructions_per_second used for these benchmarks aren't directly count of instructions ... but number of dhrystone iterations compared to the base 370/158 count ... taken to be one MIPS. there are "dhrystone mips" published for a large number of different CICS and RISC processor. part of the issue is that RISC technologies had significant performance advantage over i86 systems for a long time ... out-of-order execution, speculative execution, branch prediction, etc ... in part compensating for increasing mismatch between processor speed and memory access latency ... current access latency to memory measured in count of processor cycles is similar to 60s access latency to disk measured in 60s processor cycles (in that sense, out-of-order execution is similar to 60s multitasking). out-of-order exectuion in pipelines was used in 360 & 370 195 ... however, it didn't have branch prediction and/or speculative execution ... so conditional branches drained the pipeline. Specially tuned codes kept the execution units busy at peak throughput ... but most codes only ran 1/2 throughput. I got asked to help with a project for hyperthreading 370/195 ... simulating two processors ... two instruction streams had chance of keeping 195 execution operating at peak throughput ... although it never shipped. for the past several generations, i86 server chips have moved to risc cores with hardware translating i86 instructions into risc micro-ops ... largely negating the throughput difference between i86 and risc. z196 documentation claims that half of the processor throughput improvement over z10 processor has been the incorporation of risc out-of-order execution features ... and much of the ec12 processor thruoughput improvement over z196 processor is addition of risc-like improvements. z900, 16 processors, 2.5BIPS (156MIPS/proc), Dec2000 z990, 32 processors, 9BIPS, (281MIPS/proc), 2003 z9, 54 processors, 18BIPS (333MIPS/proc), July2005 z10, 64 processors, 30BIPS (469MIPS/proc), Feb2008 z196, 80 processors, 50BIPS (625MIPS/proc), Jul2010 EC12, 101 processors, 75BIPS (743MIPS/proc), Aug2012 ... I had run precursor to dhrystone for LLNL benchmark on engineering 4341 ... LLNL was looking at getting 70 4341s for compute farm ... sort of precursor to GRID computing ... which has also subsequently morphed into CLOUD computing. http://www.garlic.com/~lynn/2006y.html#email790220 note POK 3033 reaction to the 4341 numbers in some sense was similar to some of the current mainframe FUD. at one point, POK management got the allocation for a critical 4341 manufacturing component cut in half. other old 4300 email http://www.garlic.com/~lynn/lhwemail.html#43xx other widely used benchmarks are TPC http://www.tpc.org/ and http://www.spec.org/benchmarks.html even IBM publishes results for hundreds of such benchmarks (although not for mainframes). trivia ... Jim Gray was largely responsible for TPC benchmarks. http://www.tpc.org/information/who/gray.asp I worked with him at IBM San Jose Research before he left for Tandem ... when he pawned off bunch of stuff on me ... consulting with IMS group ... interfacing to early System/R customers ... original sql/relational dbms ... some past posts http://www.garlic.com/~lynn/submain.html#systemr -- virtualization experience starting Jan1968, online at home since Mar1970 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
