>I ABEND with an S0C4 because R2 is not as I expected That is definitely not a correct statement, but since you provided no information about what really did get the PIC 4, it is hard to comment. While R13 is not part of the interface, it happens to point to an area that is in key 0 not-write-protected storage. So your STM 0,15,0(13) would not blow up. Your L would not blow up.
Register 2 is correct. If you traced your mainline you'd see that it is the value that your SETFRR expansion returned to you in register 3. On current releases, a value of x'C20' would be the value for the 3rd FRR. Having 3 FRRs is pretty unusual for non-system code. FWIW: You don't do anything that needs your "USING FRR,R15". Also, if you do not have a system lock, are not disabled, and are not SRB mode and there are no previous FRRs that were set properly your SETFRR invocation is incorrect and your FRR may be deleted by the system at any time, such as an undispatch. EUT=YES is required in such cases. Peter Relson z/OS Core Technology Design ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
