Tom Marchant wrote:
On Tue, 4 Feb 2014 10:10:39 -0600, Mike Schwab wrote:
I think a table of the shortest possible execution times for an
instruction would be useful, how many operands it uses, and at the end
a list of how much longer a fetch takes if an operand is not stored in
the fastest level of cache.
John Eels had a SHARE presentation a couple of years ago where he described the
cost of going to memory. See page 88 of this:
https://share.confex.com/share/119/webprogramschedule/Handout/Session11718/SHARE
119 Session 11718 Presentation.pdf
I don't remember what processor this information referred to. Bottom line is
that when the data comes from L1 cache, it is available during the same machine
cycle. If it has to come from main storage, it takes about 850 machine cycles.
That example was deliberately both (a) simplified and (b) made generic
(its purpose was to illustrate the "why" for HiperDispatch in a
conceptual way). In reality, there are multiple possible latencies for
many of the levels of the cache and within the real memory hierarchy as
well. The concepts are sound but don't rely on the numbers as gospel.
Also, if I recall correctly, average memory latency is more like 950
cycles on current processors.
--
John Eells
z/OS Technical Marketing
IBM Poughkeepsie
[email protected]
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