> Starting with the zEC12 generation the following instructions are actually "executed" in the register renaming > stage of the pipeline (where "R" is the same register number for a given instruction): XR R,R; SR R,R; SLR R,R; ...
Seems mighty close to me ... Charles -----Original Message----- From: IBM Mainframe Discussion List [mailto:[email protected]] On Behalf Of John Gilmore Sent: Wednesday, June 04, 2014 3:53 PM To: [email protected] Subject: Re: XR vs SR The fact that the System/370 Model 145 instruction timings are later than those for the System/360 does not enhance their value. Some simple souls judge that later is always better; but, while this is certainly true for a loaf of bread, the inference from such examples to current instruction timings is faulty. Special casing/optimizing is pervasive in the imnplementations of z/Architecture instructions; and here in particular the two cases | SR Ri,Ri | XR Ri,Ri and | SR Ri,Rj i ¬= j | XR Ri,Rj i ¬= j are trivially easy to distinguish at the hardware level. There is indeed evidence, very persuasive but not unfortunately conclusive evidence, that the two register-zeroing special cases are identified and optimized on some and perhaps all z/Architecture models. Moreover, while reading things into other people's posts is always a perilous undertaking, it seems to me that some authoritative posts in this thread have come about as close to saying this as the proprieties involved make possible. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
