sipp...@sg.ibm.com (Timothy Sipples) writes:
> The IBM z13's ~139 SIMD instructions are different and new, yes. I expect
> that they represent a perfect functional superset of the long ago
> discontinued S/390 Vector Facility. However, it's probably not particularly
> useful to draw many parallels (!) with that older product. Yes, they are
> very different. As one example, every IBM z13 processor core incorporates
> the new SIMD instructions as a standard included feature. That's a much
> different, much lower latency design than the old, optional S/390 Vector
> Facility.
>
> If you have older code that was able to exploit the S/390 Vector Facility,
> I expect you could adapt it to exploit the new SIMD instructions. IBM's
> latest compilers can often help. However, you can do much, much more with
> the new instructions. Please see my other post about the IBM MASS and ATLAS
> libraries, for example. This IBM "redpiece" introduction is also a good,
> quick read:

the 3090 processor engineers complained some about adding vector to
3090. their claim was big part of vector was that floating point
processing was so slow ... that the typical memory bus utilization was
very low ... as a result it was possible to have large number of
floating point execution units running concurrently and still not
saturate the memory bus. they claimed that they had improved 3090
floating point processing ... so that scalar floating point was capable
of keeping memory bus busy. they felt that adding vector to 3090 was
pure marketing (since most applications would saturate memory bus just
doing scalar floating point ... and adding additional concurrent
floating point execution units would rarely increase effective
throughput).

these days the massive supercomputers have both the data and the
execution split across tens of thousands of systems.

SIMD greatly expanded type of things being done
http://en.wikipedia.org/wiki/Streaming_SIMD_Extensions

part of this is that number of chip transisters have exploded and they
are constantly looking for what they can do with all those transisters
(other than design complexity, little incremental cost ... even that is
mitigated with standard chip design libraries)

-- 
virtualization experience starting Jan1968, online at home since Mar1970

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