Not so simple anymore. "How long does a store halfword take?" used to be a question that had an answer. It no longer does.
My working rule of thumb (admittedly grossly oversimplified) is "instructions take no time, storage references take forever." I have heard it said that storage is the new DASD. This is true so much that the z13 processors implement a kind of "internal multiprogramming" so that one CPU internal thread can do something useful while another thread is waiting for a storage reference. Here is an example of how complex it is. I am responsible for an "event" or transaction driven program. I of course have test programs that will run events through the subject software. How many microseconds does each event consume? One surprising factor is how fast do you push the events through. If I max out the speed of event generation (as opposed to say, one event tenth of a second) then on a real-world shared Z the microseconds of CPU per event falls in HALF! Same exact sequence of instructions -- half the CPU time! Why? My presumption is that because if the program is running flat out it "owns" the caches and there is much less processor "wait" (for instruction and data fetch, not ECB type wait) time. Charles -----Original Message----- From: IBM Mainframe Discussion List [mailto:[email protected]] On Behalf Of Thomas Kern Sent: Wednesday, December 23, 2015 5:28 PM To: [email protected] Subject: Re: Is there a source for detailed, instruction-level performance info? Perhaps what might be useful would be an assembler program to run loops of individual instructions and output some timing information. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
