On Thu, Dec 24, 2015 at 12:47 PM, Anne & Lynn Wheeler <[email protected]> wrote:
>
<deleted>
> risc has been doing cache miss compensation for decades, out-of-order
> execution, branch prediction, speculative execution, hyperthreading ...
> can be viewed as hardware analogy to 60s multitasking ... given the
> processor something else to do while waiting for cache miss. Decade or
> more ago, some of the other non-risc chips started moving to hardware
> layer that translated instructions into risc micro-ops for scheduling
> and execution ... largely mitigating performance difference between
> those CISC architectures and RISC.
>
<deleted>
>
> as an aside, 370/195 pipeline was doing out-of-order execution ...  but
> didn't do branch proediction or speculative execution ... and
> conditional branch would drain the pipeline. careful coding could keep
> the execution units busy getting 10MIPS ... but normal codes typically
> ran around 5MIPS (because of conditional branches). I got sucked into
> helping with hyperthreading 370/195 (which never shipped), it would
> simulate two processors with two instructions streams, sets of
> registers, etc ... assuming two instruction streams, each running at
> 5MIPS would then keep all execution units running at 10MIPS.
>
<deleted>
>
> --
> virtualization experience starting Jan1968, online at home since Mar1970
>
https://en.wikipedia.org/wiki/IBM_7030_Stretch
First computer to implement: Multiprogramming, memory protection,
generalized interrupts, the eight-bit byte, instruction pipelining,
prefetch and decoding, and memory interleaving.

If branch predicting is a big hang up, the obvious solution is to
start processing all possible outcomes then keep the one that is
actually taken.  I. E.  B OUTCOME(R15) where R15 is a return code of
0,4,8,12,16.


-- 
Mike A Schwab, Springfield IL USA
Where do Forest Rangers go to get away from it all?

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