On Mon, 28 Dec 2015 11:02:15 -0600, Jerry Callen <[email protected]> wrote:
>I'm not really after detailed timing. I'm looking for implementation details >of the same sort used by compiler writers to guide selection of instruction >sequences, where the guiding principle is, "How can I avoid pipeline stalls?" >As I noted, several SHARE presentations contain SOME of this information, >which I've already benefited from, but I'm looking for more. Just remember that your machine runs more than one thing at a time, and trying to over-engineer a solution may end up being suboptimal. Nice for single-thread performance, but it may be irrelevant in terms of overall throughput. If caches are sufficiently polluted by other LPARs, you may find no advantage. Someday they may even violate the law of causality. Who knows.... Every processor family has different behaviors. The longevity of the z architecture can be attributed to the fact that we don't get overly carried away trying to teach the machines to sit up and beg. At some point, it's "fast enough" and making it go faster is just an academic exercise. >I'm still hoping that someone will reveal the existence of a document intended >for compiler writers... Folks who participate in PWD may have access to that kind of information -- I don't know. If you participate in Linux GCC development, then you can see what IBM loads upstream for new processors. Alan Altmark IBM ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
