[email protected] (Mike Myers) writes:
> A few years ago, we pretty much dropped the concept of MIPS, changing
> it from Millions of Instructions Per Second to Meaningless Indicator
> of Processor Speed. Simply compare the accomplishment of a single line
> of assembler, such as comparing LR to CFC (Compare and Form Codeword)
> or UPT (UPdate Tree). It becomes obvious that a lot more LRs (or
> similar RR instructions) can be accomplished per second than the
> number of CFCs or UPTs in the same interval of time on the same
> machine.

for a long time, industry standard for MIPS is number of benchmark
interations compared to baseline runs on 370/158-3 & vax-11/780 (not
actually count of instructions)
http://en.wikipedia.org/wiki/Instructions_per_second

IBM numbers:

z900,  16 processors, 2.5BIPS (156MIPS/proc), Dec2000
z990,  32 processors, 9BIPS, (281MIPS/proc), 2003
z9,    54 processors, 18BIPS (333MIPS/proc), July2005
z10,   64 processors, 30BIPS (469MIPS/proc), Feb2008
z196,  80 processors, 50BIPS (625MIPS/proc), Jul2010
EC12, 101 processors, 75BIPS (743MIPS/proc), Aug2012

z13 published refs is 30% move throughput than EC12 or about 100BIPS
with 40% more processors ... or about 710MIPS/proc (which would be per
processor decline from EC12).

IBM previous references were that at least half of the per processor
throughput increase from z10 to z196 was introduction of out-of-order
execution and other features that have been part of other platforms for
decades.  This is critical because of the increasing mismatch between
processor machine cycle and memory access latency ... aka memory access
latency when measured in count of processor cycles is compareable to
1960s disk access latency when measured in count of 1960s processor
cycles (effective throughput is increasingly dependent on how memory
access latency is handled).

-- 
virtualization experience starting Jan1968, online at home since Mar1970

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