arno...@us.ibm.com (Todd Arnold) writes: > 360 processors with special microcode were used in a number of things. > Early in my career, I worked on development of the IBM 3890 high-speed > check sorter. (https://en.wikipedia.org/wiki/IBM_3890) The controller > in that sorter was a 360 mod 25, with all the code written in native > microcode - no 360 instruction set. It turned out to be very fast, > and it was many years before IBM was able to find anything to replace > that old mod 25 with its core memory.
re: http://www.garlic.com/~lynn/2017c.html#80 Great mainframe history(?) http://www.garlic.com/~lynn/2017c.html#81 GREAT presentation on the history of the mainframe http://www.garlic.com/~lynn/2017c.html#82 Great mainframe history(?) http://www.garlic.com/~lynn/2017c.html#83 Great mainframe history(?) http://www.garlic.com/~lynn/2017c.html#84 Great mainframe history(?) http://www.garlic.com/~lynn/2017c.html#85 Great mainframe history(?) nearly all 360s & 370s had integrated channels (engine was shared between simulating 360/370 instructions and running channel microcode) ... it was only the high-end machines that had dedicated external channles 360/65 & above, 165/168, etc. boeblingon got their hands slapped by corporate for the 370/115 & 370/125. The 370/115 had nine-position memory bus for microprocessors ... all identical ... one microprocessor was programmed for simulating 370 instructions and one or several other microprocessors programmed with controller microcode (i.e. not only integrated channels, but also integrated controllers). The 370/125 was identical to the 370/115 except the microprocessor running the 370 instruction simulation microcode was 50% faster (than the othere microprocessors). Very few customer 115/125 configurations had more than 2-3 controller microprocessors, so they suck me into doing a 5-way SMP multiprocessor design for 370/125 (I also do a bunch of enhancements including queued IO/interrupt akin to what is later seen with 370/xa, I also drop microcode queued interface for multiprocessing dispatching). Endicott also sucks me into do a lot of work on the microcode enhancements for 138/148. Endicott then complains tht the 5-way 370/125 SMP has better performance and better price/performance than 370/148 and I'm required in escalation meetings to argue both sides. Endicott wins ... and the 5-way SMP 370/125 is never announced. In the late 70s, there was an effort to replace the myriad of different internal microprocessors with 801/risc (Illiad) ... to simplify the enormous development & programming environments for each unique microprocessor ... aka the 4361&4381 followon to 4331&4341, the S/38, nearly every controller. etc. The followon to the displaywriter was also going to be 801/risc romp. In any case, all of these efforts floundered for various reasons. The channel latency processing of the 370/158 intergrated channels was much slower than the high end external channels ... characteristic which is then carried over to the whole 303x family (3031, 3032, 3033). An example was that even the 4341 integrated channel with minor tweak was able to handle the 3880/3380 3mbyte/sec speed (and could be used in bldg14&15 for 3880/3380 testing). trivia: 138/148 microcode enhancement. Typical 370 (vertical) microcode simulation ran avg. of ten native instructions for every 370 instruction. I was told that there was 6kbytes worth of available microcode space ... and the objective was identify the highest used 6kbytes of supervisor code for dropping into microcode for 10:1 speedup. old post that 6kbytes of kernel highest used pathlength accounted for 79.55% of kernel processing time (reduced to 8% when dropped into native microcode, 10:1 speedup) http://www.garlic.com/~lynn/94.html#21 other trivia: low&mid-range was vertical microcode ... so those 360&370 machines were little like the Hercules simulation (and native MIP rate was ten times faster than 370 MIP rate). The high-end machines were horizontal micrcode ... and rather than measured in avg native instructions to 360/370 instructions ... high-end machines were measured in avg. machine cycles per 360/370 instructions (in part because of high level of hardware integration and overlap). Part of the move from 370/165 to 370/168 was replacing the 2mic memory with 400ns memory (cache miss latency reduced). The other part was optimizing the horizontal microcode reducing the avg. machine cycles from 2.1 to 1.6. 3033 started out with moving 168 logic to 20% faster chips ... but they also further optimized horizontal microcode getting down close to avg of one machine cycle per 370 instruction. -- virtualization experience starting Jan1968, online at home since Mar1970 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
