Dave Rivers: You may find the following commentary to be relevant. -Dave Cole
*************************************************************
* * Z21-1505F
* Save floating point and vector registers (when the * Z21-1505F
* hardware support is present AND!!! their use has been * Z21-1505F
* activated in the target thread). * Z21-1505F
* * Z21-1505F
*************************************************************
* * 04/09 Z1A
* This from Peter Morrison <[email protected]>: * 04/09 Z1A
* * 04/09 Z1A
* "Whereas the old FP regs (0/2/4/6) are saved in the * 04/09 Z1A
* TCB (always), the advanced FP stuff (the other 12 FP * 04/09 Z1A
* regs and the FPC reg) are saved in the STCB. But, * 04/09 Z1A
* ONLY IF necessary. There is a bit (STCBFPFL/STCBBFP * 04/09 Z1A
* X'80') that if set on, will cause MVS to save/restore * 05/14 Z21
* all state. * 04/09 Z1A
* * 04/09 Z1A
* "MVS leaves the relevant CR0 bit off, and any attempt * 04/09 Z1A
* to execute an FP instruction that references one of * 04/09 Z1A
* the 12 extra regs, or BFP, or DFP, will cause a pgm * 04/09 Z1A
* check (data exception). MVS sees that, sets on the * 04/09 Z1A
* STCB flag, sets on the CR0 flag, and resumes * 04/09 Z1A
* execution. From that point on, any TCB context * 04/09 Z1A
* save/restore will save/restore all FP state. * 04/09 Z1A
* * 04/09 Z1A
* So if AFP hardware has not yet been used in the current * Z21-1505F
* thread, then I must not attempt to save any AFP registers * Z21-1505F
* because the mere act of doing so will cause z/OS to turn * Z21-1505F
* AFP support on, and that could be an unplesant surprise * Z21-1505F
* to the target program. * Z21-1505F
* * 04/09 Z1A
************************************************************* 04/09 Z1A
* * Z21-1505F
* Ditto for the SIMD vector registers... If their use has * Z21-1505F
* not yet been activated in the target thread, then I must * Z21-1505F
* not attempt to save them. * Z21-1505F
* * Z21-1505F
************************************************************* Z21-1505F
Dave Cole
ColeSoft Marketing
414 Third Street, NE
Charlottesville, VA 22902
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At 9/26/2017 03:37 PM, Jim Mulder wrote:
In the old days, you would check
CVTBFP EQU X'10' Binary Floating Point support @MGA
* (simulated unless CVTBFPH is on) @MGA
That bit is always on with OS/390 2.6 or higher. You definitely
should not look at the CR0 bit.
Jim Mulder z/OS Diagnosis, Design, Development, Test IBM Corp.
Poughkeepsie NY
IBM Mainframe Discussion List <[email protected]> wrote on
09/26/2017 12:47:40 PM:
> From: Thomas David Rivers <[email protected]>
> To: [email protected]
> Date: 09/26/2017 03:29 PM
> Subject: Is the AFP control bit (big #13 in CR0) testable in an
application?
> Sent by: IBM Mainframe Discussion List <[email protected]>
>
> I was hoping to determine if a program is allowed
> to use the Additional Floating Point (AFP) registers.
>
> There are two qualifications for this; first the "basic floating point
> extensions"
> has to be installed (which can be assumed after OS/390 2.6) and
> second, the AFP CONTROL BIT of Control Register 0 has to be enabled
> (bit #13.)
>
> So - while the hardware allows it, it's possible - for some reason or
> other -
> the control register disallows it.
>
> I'm looking around in the various locations (CVT, PSA, etc...) and
hunting
> for a mechanism where an application program can ask "Am I allowed to
> use all 16 floating-pt registers, or am I restricted to the traditional
4?"
>
> Is there an assembler service somewhere that provides the value of
control
> registers? You can just use STORE CONTROL (STCTL) instruction as it is
> privileged.
>
> - Many thanks -
> - Dave Rivers -
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