[email protected] (Edward Finnell) writes:
> For decades MVS has honored the concept of public, Storage and private
> DASD. Numerous SHARE papers on how to configure DASD subsystems in
> order to reduce contention and optimize thruput. WSC under Ray Wicks
> produced many of them. One of my favorites was the 'The Big
> Pitcher'. Properly administered SMS can enhance the basic concepts and
> augment them with storage overflow.
>  
> If we had more info on the problem better suggestions could be
> provided. One of the old tricks was to preallocate sortwks and pass
> them thru the life of the job. No need to worry about vol=ref

back when CKD were real ... (rather than various kinds of simulation on
industry fixed-block disks ... all that rotational positioning and arm
motion, track lengths ... are all fiction) ... I was increasingly
pointing out that disk wasn't keeping up with computer technology and by
the early 80s was saying that disk relative system throughput had
declined by a factor of ten times since the 60s (disk throughput
increased 3-5 times, processor and memory throughput increased 40-50
times).

Some disk division executive took exception and assigned the division
performance group to refute the statements. after several weeks they
eventually came back and effectively said that I had slightly under
stated the problem. The analysis was then respun as disk configuration
recommendations for improving system throughput ... SHARE presentation
B874. old post with part of the early 80 comparison
http://www.garlic.com/~lynn/93.html#31
old posts with pieces of B874
http://www.garlic.com/~lynn/2001l.html#56
http://www.garlic.com/~lynn/2006f.html#3

note that memory is the new disk ... current latency for cache miss,
memory access ... when measured in count of processor cycles is similar
to 60s disk latency when measured in 60s processor cycles ....  it is
part of the introduction of out-of-order execution, branch prediction,
speculative execution, hyperthreading ... stuff that can go on while
waiting on stalled instruction (waiting for memory on cache miss)
.... these show up in z196 (accounting for at least half the performance
improvement over z10) ... much of this stuff have been in other
platforms for decades.

trivia: 195 pipeline had out-of-order execution ... but no branch
prediction and/or speculative execution ... so conditional branches
stalled the pipeline, most applications would only ran at half 195 rated
performance. I got dragged into proposal to hyperthread 195 ... two
instruction streams simulating multiprocessor ... two simulated
processors running programs around half throughput ... then would keep
195 running at rated speed. It was never done ...

IBM hyper/multi threading patents mentioned in this post about the end
of ACS/360
https://people.cs.clemson.edu/~mark/acs_end.html

from Amdahl interview in the above:

IBM management decided not to do it, for it would advance the computing
capability too fast for the company to control the growth of the
computer marketplace, thus reducing their profit potential. I then
recommended that the ACS lab be closed, and it was.

... snip ...

end of the article has some of the acs/360 features that show up more
than 20yrs later in es/9000.

-- 
virtualization experience starting Jan1968, online at home since Mar1970

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