On 3/4/2019 5:39 AM, R.S. wrote:
W dniu 2019-03-03 o 17:07, Christopher Y. Blaicher pisze:
ZIIP and ZAAP processors always run at full speed, even when running
on a sub-capacity box.
One thing, among many, I don't know is how IBM implements
sub-capacity. Slow the clock speed? Skip cycles?
All processors, including subcapacity CPs run at the same speed, which
is different for big box and small (BC) box.
How subcapacity CP makes the subcapacity? By stealing cycles, imagine
there's hidden LPAR with some fixed weigth.
IMHO that's not a good analogy. The cycles aren't "stolen" in a manner
at all similar to a so-called "soak" LPAR.
Each CP has a timed "service loop" with a housekeeping routine --
implemented in millicode -- that handles interrupts, SIGP instructions,
etc. When the housekeeping is finished, the CP runs instructions for the
remainder of the interval.
One of the last things in the housekeeping routine is a coded loop
(probably using an ordinary BCT instruction) that iterates "N" times
where the value of "N" is a constant that varies depending on the
sub-capacity model.
So a better analogy might be that each CP is going around a race track
and pulls into the pits on each lap. After servicing, sub-capacity
models are held in the pits for awhile before they're allowed back on
the track.
--
Phoenix Software International
Edward E. Jaffe
831 Parkview Drive North
El Segundo, CA 90245
https://www.phoenixsoftware.com/
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