Thanks everyone for your input. I learned a lot from these responses. I
actually meant to write ADD HALFWORD IMMEDIATE in my original email. I was
surprised to hear about LA. I had assumed that direct register manipulation
was the fastest.

On the topic of cache, how do I know that my literal pool is actively
cached at execution of a certain instruction? What would cause the hardware
to move my literal pool out of cache?

Thank you,

Brian Chapman

On Tue, Aug 13, 2019 at 10:17 AM Charles Mills <> wrote:

> I second everything Chris Blaicher says. You just cannot say how long an
> instruction takes. Let me give you an example. (The example is based on
> theoretical concepts and has not been tested or benchmarked.)
> Let's say you had some tight loop that was executed many thousands or
> millions of times. Let's say you were to insert into the code somewhere the
> following instruction: L R0,=F'1', and let's assume that R0 is not in use
> at that point so this addition does not change the logic of the program.
> If the insertion were between some compare and an immediately following
> conditional jump or branch, and the literal pool were already in the data
> cache, then the impact of the added instruction might literally be zero.
> The processor could execute it entirely while it was waiting for the
> condition code to "settle" anyway. You might in a benchmark see absolutely
> no discernible change. So it would be fair to say that the LOAD took no
> time at all.
> On the other hand if you inserted it at some other point in the code,
> where the literal pool was not in the cache already, or worse, was always
> at that point in the flow cached for write access on some other processor,
> then the impact might be quite noticeable (assuming enough executions of
> the loop -- on a human scale of time, ANY instruction takes no noticeable
> time at all).
> With regard to your specific questions, I think of a L/ST sequence as
> being faster than an MVC for four aligned bytes, but I am not certain that
> is true. (MUCH faster? I seriously doubt it.) Other factors such as those
> discussed in my little example above are much more significant.
> I am told that LA is "worse" than other "increment" instructions because
> it involves an index register. The instruction to use to increment a
> register is undoubtedly AHI for reasons that I believe Chris mentions. AH
> (or A) is certainly the worst of the lot because it involves storage access.
> My (admittedly grossly oversimplified) rule of thumb when coding is
> "instructions take no time at all; memory accesses take forever."
> Charles
> -----Original Message-----
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On
> Behalf Of Brian Chapman
> Sent: Monday, August 12, 2019 5:48 PM
> Subject: Instruction speeds
> Hi everyone,
> I did some searching, but I didn't find anything that really discussed this
> on the topic that I'm interested. Is there anything published that compares
> the cycle times of the most used instructions?
> For example; moving an address between areas of storage. I would assume
> that executing a LOAD and STORE would be much quicker than executing a MVC.
> Or executing a LOAD ADDRESS to increment a register instead of ADD HALF
> Or does this really matter as much as ordering the instructions so they are
> optimized for the pipeline?
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