um how much memory is defined? Is there a chance of IPLing in a 2nd level machine to see if instruction simulation masks the problem? David
________________________________ From: The IBM z/VM Operating System on behalf of Martin, Terry R. (CMS/CTR) (CTR) Sent: Tue 9/23/2008 6:09 PM To: [email protected] Subject: Re: [IBMVM] WAIT STATE 9003 This is a separate VM LPAR there is no second level. I am running a 2094-711 (z9) and it is an IFL. Thank You, Terry Martin Lockheed Martin - Information Technology z/OS & z/VM Systems - Performance and Tuning Cell - 443 632-4191 Work - 410 786-0386 [EMAIL PROTECTED] ________________________________ From: The IBM z/VM Operating System [mailto:[EMAIL PROTECTED] On Behalf Of David Kreuter Sent: Tuesday, September 23, 2008 6:05 PM To: [email protected] Subject: Re: WAIT STATE 9003 what model cpu is it? Does the same CPLOAD MODULE IPL in a 2nd level system? David ________________________________ From: The IBM z/VM Operating System on behalf of Martin, Terry R. (CMS/CTR) (CTR) Sent: Tue 9/23/2008 5:45 PM To: [email protected] Subject: [IBMVM] WAIT STATE 9003 Hi Here we go again: I am receiving a WAIT STATE 9003 while trying to IPL my test LPAR (VM5.3). I have no idea what/why he is trying to do at this point with the PROCESSOR. Does anyone know a symptom that would cause this wait state? HCP9003W PROCESSOR QUIESCED -- VARY OFFLINE Explanation: A VARY OFFLINE PROCESSOR command has been received for a processor. System Action: o When the master processor is varied offline, the normal system action is for the master processor to enter a stopped state using a SIGP CPU Reset. If an attempt is made to restart the master processor, it will load a disabled wait-state PSW, wait-state code 9003. Processing continues on the remaining processors. o A processor being varied offline that is not the master processor loads a disabled wait-state PSW, wait-state code 9003. Processing continues on the remaining processors. System Action: o When the master processor is varied offline, the normal system action is for the master processor to enter a stopped state using a SIGP CPU Reset. If an attempt is made to restart the master processor, it will load a disabled wait-state PSW, wait-state code 9003. Processing continues on the remaining processors. o A processor being varied offline that is not the master processor loads a disabled wait-state PSW, wait-state code 9003. Processing continues on the remaining processors. User Response: None. Operator Response: None. Thank You, Terry Martin Lockheed Martin - Information Technology z/OS & z/VM Systems - Performance and Tuning Cell - 443 632-4191 Work - 410 786-0386 [EMAIL PROTECTED]
