On Thu, Jun 23, 2011 at 16:54, Tavish Naruka <[email protected]> wrote:

> hi! I am making a makefile in which i need to include files for compilation
> and includes depending on the name of the library. I know where the library
> is if i know the name.
>
> genlibs:
> LIB_NAMES=$(shell python genmake.py $(TARGET).pde $(ARDUINO_LIB_SRC))
> @for i in $(LIB_NAMES); do \
> EXTRA_LIBS_CXX  +=    $(wildcard $(ARDUINO_LIB_SRC)/$$i/*.cpp) $(wildcard
> $(ARDUINO_LIB_SRC)/$$i/utility/*.cpp); \
> EXTRA_LIBS_C      +=  $(wildcard $(ARDUINO_LIB_SRC)/$$i/*.c) $(wildcard
> $(ARDUINO_LIB_SRC)/$$i/utility/*.c); \
> INCLUDE      +=  $(addprefix -I, $(dir $(wildcard
> $(ARDUINO_LIB_SRC)/$$i/*)) $(dir $(wildcard
> $(ARDUINO_LIB_SRC)/$$i/utility/*))); \
> LINK_INCLUDE+=$(addprefix -L, $(dir $(wildcard $(ARDUINO_LIB_SRC)/$$i/*))
> $(dir $(wildcard $(ARDUINO_LIB_SRC)/$$i/utility/*))); \
> done
>
> I need variable definitions in a loop, EXTRA_LIBS += something to append to
> the variable. Also, is there some other way to do what i am trying to do?
>

The way I know such things are done is through different ifeq blocks, I am
not sure the Make architecture supports loops.



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