I don't want to give tutorials as part of tips but some of you may like it.
I want to teach make(1), the program to build source code. make knows only directories. It looks for a file called Makefile or makefile or whatever. In all cases I have seen only Makefile. A bunch of rules are organized like this: target : source dependencies ... Some rules have a method to tell make how to create target from the source. A good example is this one: foo: foo.c <TAB> $(CC) $(CFLAGS) $< -o $@ If this is too much for you, how about this? foo : foo.c <TAB> gcc -lm foo.c -o foo Both are same. Except that in the former you need to define variables like this usually done at the top of the Makefile. CC=gcc CFLAGS=-lm $@ gets assigned to the right side of the ':' of the rule, the source files or dependencies. And $< is the target specification. Make always needs a TAB character to begin the actions after a dependency specification. It is a deep topic and I will wind up this session with a mention of the .PHONY pseudo rule. You say, .PHONY: clean all in the Makefile to indicate that the rules "clean" and "all" are not real targets. They don't correspond to files on the file system but names for rules. This is to avoid collision when you actually have filenames by that name. Usually you don't and it is good to know what this means at least for curiosity's sake when you read other people's Makefiles. -Girish -- Gayatri Hitech web: http://gayatri-hitech.com SpamCheetah Spam filter: http://spam-cheetah.com _______________________________________________ To unsubscribe, email [email protected] with "unsubscribe <password> <address>" in the subject or body of the message. http://www.ae.iitm.ac.in/mailman/listinfo/ilugc
