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11th IEEE International
Workshop on Rapid System Prototyping
Paris, France, June 21-23 2000
http://www-src.lip6.fr/rsp
To have information about registration, conference site, hotel reservation and
social events look at the RSP web site (http://www-src.lip6.fr/rsp).
Presented Papers
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Codesign methodologies
1. A Methodology for Implementing Medium Access Protocols Using a General
Parameterized Architecture (M. Iliopoulos & T. Antonakopoulos)
2. Design Space Exploration for Hardware/Software Codesign of
Multiprocessor Systems
(A. Baghdadi, N-E. Zergainoh, W. Cesario, A.A. Jerraya & T. Roudier)
3. Efficient Modeling of Preemption in a Virtual Prototype (Johan Cockx)
4. Combining Virtual Benchmarking with Rapid System Prototyping for
Real-Time Embedded Multiprocessor Signal Processing System Codesign
(R. Janka & L. Wills)
Software methodologies
1. A Risk Assessment Model for Software Prototyping Projects
(J-C. Nogueira, Luqi & S. Bhattacharya)
2. Processor Models for retargetable tools (R. Moona)
3. MODUS: Integrated Behavior-Oriented Model for Rapid Prototyping
(Y. Gonzalez Arechavala & F. de Cuadra Garcia)
4. Equivalence Checking of Two Statechart Specifications
(M-H. Park, K_S. Bang, J-Y. Choi & I. Kang )
5. Intuitive Design of Complex Real-Time Control Systems
(M. Dimmler & Y. Piguet)
Tools
1. Cycle-true Simulation of the ST10 microcontroller
(L. Gauthier & Ahmed Amine Jerraya)
2. Hardware/Software Co-Design of a Java Virtual Machine,
(K. Kent & M. Serra)
3. Emulator environment based on an FPGA prototyping board
(K-S. Oh, S-Y. Yoon & S-I. Chae )
4. A Comprehensive Prototyping-Platform for Hardware-Software Codesign
(A. Koch)
Real time systems
1. Quasi-static Scheduling of Reconfigurable Dataflow Graphs for DSP
Systems (B. Bhattacharya & S. Bhattacharyya)
2. A design methodology for Hardware Prototyping of integrated AC drive
control: Application to Direct Torque Control of an induction machine
(P. Poure, F. Aubepart & F. Brun)
Hardware methodologies
1. Speeding up hardware prototyping by incremental Simulation/Emulation
(N. Canellas & J. M. Moreno)
2. Mapping a High-Speed Wireless Communication Function to the
Reconfigurable J-Platform,
(V. Jain)
3. A Prototype of an AAL for High Bit Rate Real-time Data Transmission
System over ATM Networks Using a RSE CODEC,
(D. Eilers, R. Knorr, G. Kerner, A. Plankl & A. Voglgsang)
4. The FLYSIG Prototyping Approach
(W. Hardt, B. Kleinjohann & A. Rettberg)
Code Generation
1. A Verilog to C Compiler (D. Greaves)
2. Using MetaScribe to prototype an UML to C++/Ada95 code generator
(D. Regep & F. Kordon)
3. An Evaluation of Code Generation Strategies Targeting Hardware
for the Rapid Prototyping of SDL-Specifications
(A. Muth, T. Kolloch & T. Maier-Komor)
Methodologies
1. Integration and Evolution of Model-Based Tool Prototypes
(A. Bredenfeld)
2. Coprocessor Synthesis of Multirate System Using Static Scheduling
Theory (R. Kamdem & A. Fonkoua)
3. Automated Communication Synthesis for Architecture-precise Rapid
Prototyping of Real-time Embedded Systems
(F-M. Renner, J. Becker & M. Glesner)
4. Simulation and Real-time Rapid Prototyping of flexible
Systems-on-a-Chip for Future Mobile Communication Systems
(J Becker, L. Kabulepa, F-M. Renner & M. Glesner)
Real time systems
1. Reconfigurable Instruction Set Processors, A Survey
(F. Barat & R. Lauwereins)
2. Highly Configurable Control Board: a Tool and a Design Experience
(E. de la Torre, T. Riesgo, J. Uceda, E. Macip & M. Rizzi)
Hardware systems
1. Power-Constrained Block-Test List Scheduling
(V. Muresan, X. Wang, V. Muresan & M. Vladutiu)
2. Adaptive FPGA Placement by Natural Optimisation
(J. de Vicente, J. Lanchares & R. Hermida)
3. A Hardware Virtual Machine to Support Networked Reconfiguration
(Y. Ha, H. De Man, P. Schaumont, M. Engels, S. Vernalde
& F. Potargent)
4. FPGA Technology Snapshot : Current Devices and Design Tools
(H. Krupnova & G. Saucier)
Methodologies
1. Validation of Link Layer Synthesizable Core - a prototyping case study
(Prasad P G)
2. Hardware Accelerated Estimation of Multiplexer-Introduced Loss for
MPEG-4 Data Streams,
(U. Mayer & M. Glesner)
Embedded systems
1. Efficient Clock-Cycle Precise Simulation at Architecture Level in C++
(G. Eggers & H. Zeidler-)
2. Embedded System Architecture Design Based on Real-Time Emulation
(C. Nitsch, K. Weiss, T. Steckstor & W. Rosenstiel)
