On Sat, 17 Apr 2010 15:12:03 +0200, Daniel Vetter <[email protected]> wrote: > Current code is definitely crap: Largest pitch allowed spills into > the TILING_Y bit of the fence registers ... :( > > I've rewritten the limits check under the assumption that 3rd gen hw > has a 3d pitch limit of 8kb (like 2nd gen). This is supported by an > otherwise totally misleading XXX comment. > > This bug mostly resulted in tiling-corrupted pixmaps because the kernel > allowed too wide buffers to be tiled. Bug brought to the light by the > xf86-video-intel 2.11 release because that unconditionally enabled > tiling for pixmaps, relying on the kernel to check things. Tiling for > the framebuffer was not affected because the ddx does some additional > checks there ensure the buffer is within hw-limits. > > v2: Instead of computing the value that would be written into the > hw fence registers and then checking the limits simply check whether > the stride is above the 8kb limit. To better document the hw, add > some WARN_ONs in i915_write_fence_reg like I've done for the i830 > case (using the right limits). > > Signed-off-by: Daniel Vetter <[email protected]> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27449 > Tested-by: Alexander Lam <[email protected]> > Cc: [email protected]
Ignore previous response. Here's exactly the patch I wanted. Applied to for-linus.
pgpnCeEP0RkkC.pgp
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