On Tue, Oct 11, 2016 at 02:21:50PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
> 
> Saves 944 bytes of .rodata strings and 128 bytes of .text.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com>

Reviewed-by: David Weinehall <david.weineh...@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h         | 2 +-
>  drivers/gpu/drm/i915/i915_gem_fence.c   | 2 +-
>  drivers/gpu/drm/i915/i915_gpu_error.c   | 4 ++--
>  drivers/gpu/drm/i915/intel_crt.c        | 6 +++---
>  drivers/gpu/drm/i915/intel_display.c    | 6 +++---
>  drivers/gpu/drm/i915/intel_dp.c         | 8 ++++----
>  drivers/gpu/drm/i915/intel_hdmi.c       | 2 +-
>  drivers/gpu/drm/i915/intel_pm.c         | 2 +-
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
>  9 files changed, 17 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 96846ecfc224..f9f9a218d5fe 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2659,7 +2659,7 @@ struct drm_i915_cmd_table {
>  #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
>                                INTEL_DEVID(dev_priv) == 0x0152 || \
>                                INTEL_DEVID(dev_priv) == 0x015a)
> -#define IS_VALLEYVIEW(dev)   (INTEL_INFO(dev)->is_valleyview)
> +#define IS_VALLEYVIEW(dev_priv)      ((dev_priv)->info.is_valleyview)
>  #define IS_CHERRYVIEW(dev_priv)      ((dev_priv)->info.is_cherryview)
>  #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
>  #define IS_BROADWELL(dev_priv)       ((dev_priv)->info.is_broadwell)
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c 
> b/drivers/gpu/drm/i915/i915_gem_fence.c
> index 8df1fa7234e8..d26768567252 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence.c
> @@ -448,7 +448,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
>       uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
>       uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
>  
> -     if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) {
> +     if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
>               /*
>                * On BDW+, swizzling is not used. We leave the CPU memory
>                * controller in charge of optimizing memory accesses without
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index d41517e11978..6eb11fd326fd 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1349,7 +1349,7 @@ static void i915_capture_reg_state(struct 
> drm_i915_private *dev_priv,
>        */
>  
>       /* 1: Registers specific to a single generation */
> -     if (IS_VALLEYVIEW(dev)) {
> +     if (IS_VALLEYVIEW(dev_priv)) {
>               error->gtier[0] = I915_READ(GTIER);
>               error->ier = I915_READ(VLV_IER);
>               error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
> @@ -1398,7 +1398,7 @@ static void i915_capture_reg_state(struct 
> drm_i915_private *dev_priv,
>               error->gtier[0] = I915_READ(GTIER);
>       } else if (IS_GEN2(dev)) {
>               error->ier = I915_READ16(IER);
> -     } else if (!IS_VALLEYVIEW(dev)) {
> +     } else if (!IS_VALLEYVIEW(dev_priv)) {
>               error->ier = I915_READ(IER);
>       }
>       error->eir = I915_READ(EIR);
> diff --git a/drivers/gpu/drm/i915/intel_crt.c 
> b/drivers/gpu/drm/i915/intel_crt.c
> index d456786f5813..d92c3edf10ff 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -253,7 +253,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
>  
>       if (HAS_PCH_LPT(dev_priv))
>               max_clock = 180000;
> -     else if (IS_VALLEYVIEW(dev))
> +     else if (IS_VALLEYVIEW(dev_priv))
>               /*
>                * 270 MHz due to current DPLL limits,
>                * DAC limit supposedly 355 MHz.
> @@ -423,7 +423,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector 
> *connector)
>       if (HAS_PCH_SPLIT(dev_priv))
>               return intel_ironlake_crt_detect_hotplug(connector);
>  
> -     if (IS_VALLEYVIEW(dev))
> +     if (IS_VALLEYVIEW(dev_priv))
>               return valleyview_crt_detect_hotplug(connector);
>  
>       /*
> @@ -850,7 +850,7 @@ void intel_crt_init(struct drm_device *dev)
>  
>       if (HAS_PCH_SPLIT(dev_priv))
>               adpa_reg = PCH_ADPA;
> -     else if (IS_VALLEYVIEW(dev))
> +     else if (IS_VALLEYVIEW(dev_priv))
>               adpa_reg = VLV_ADPA;
>       else
>               adpa_reg = ADPA;
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index d61a12dbbd72..c3fb9f700c7a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5876,7 +5876,7 @@ static void intel_update_max_cdclk(struct drm_device 
> *dev)
>                       dev_priv->max_cdclk_freq = 675000;
>       } else if (IS_CHERRYVIEW(dev_priv)) {
>               dev_priv->max_cdclk_freq = 320000;
> -     } else if (IS_VALLEYVIEW(dev)) {
> +     } else if (IS_VALLEYVIEW(dev_priv)) {
>               dev_priv->max_cdclk_freq = 400000;
>       } else {
>               /* otherwise assume cdclk is fixed */
> @@ -6840,7 +6840,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state 
> *old_crtc_state,
>       if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
>               if (IS_CHERRYVIEW(dev_priv))
>                       chv_disable_pll(dev_priv, pipe);
> -             else if (IS_VALLEYVIEW(dev))
> +             else if (IS_VALLEYVIEW(dev_priv))
>                       vlv_disable_pll(dev_priv, pipe);
>               else
>                       i9xx_disable_pll(intel_crtc);
> @@ -8906,7 +8906,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc 
> *crtc,
>  
>       if (IS_CHERRYVIEW(dev_priv))
>               chv_crtc_clock_get(crtc, pipe_config);
> -     else if (IS_VALLEYVIEW(dev))
> +     else if (IS_VALLEYVIEW(dev_priv))
>               vlv_crtc_clock_get(crtc, pipe_config);
>       else
>               i9xx_crtc_clock_get(crtc, pipe_config);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1e1ccf092e11..a2c4d5a0b704 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1350,7 +1350,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
>       } else if (IS_CHERRYVIEW(dev_priv)) {
>               divisor = chv_dpll;
>               count = ARRAY_SIZE(chv_dpll);
> -     } else if (IS_VALLEYVIEW(dev)) {
> +     } else if (IS_VALLEYVIEW(dev_priv)) {
>               divisor = vlv_dpll;
>               count = ARRAY_SIZE(vlv_dpll);
>       }
> @@ -1790,7 +1790,7 @@ static void intel_dp_prepare(struct intel_encoder 
> *encoder,
>                       trans_dp &= ~TRANS_DP_ENH_FRAMING;
>               I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
>       } else {
> -             if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev) &&
> +             if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
>                   !IS_CHERRYVIEW(dev_priv) &&
>                   pipe_config->limited_color_range)
>                       intel_dp->DP |= DP_COLOR_RANGE_16_235;
> @@ -3351,7 +3351,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>                       mask = DDI_BUF_EMP_MASK;
>       } else if (IS_CHERRYVIEW(dev_priv)) {
>               signal_levels = chv_signal_levels(intel_dp);
> -     } else if (IS_VALLEYVIEW(dev)) {
> +     } else if (IS_VALLEYVIEW(dev_priv)) {
>               signal_levels = vlv_signal_levels(intel_dp);
>       } else if (IS_GEN7(dev) && port == PORT_A) {
>               signal_levels = gen7_edp_signal_levels(train_set);
> @@ -5801,7 +5801,7 @@ bool intel_dp_init(struct drm_device *dev,
>               intel_encoder->enable = vlv_enable_dp;
>               intel_encoder->post_disable = chv_post_disable_dp;
>               intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
> -     } else if (IS_VALLEYVIEW(dev)) {
> +     } else if (IS_VALLEYVIEW(dev_priv)) {
>               intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
>               intel_encoder->pre_enable = vlv_pre_enable_dp;
>               intel_encoder->enable = vlv_enable_dp;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index c8243dc4d2b9..501334242d38 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1965,7 +1965,7 @@ void intel_hdmi_init(struct drm_device *dev,
>               intel_encoder->enable = vlv_enable_hdmi;
>               intel_encoder->post_disable = chv_hdmi_post_disable;
>               intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
> -     } else if (IS_VALLEYVIEW(dev)) {
> +     } else if (IS_VALLEYVIEW(dev_priv)) {
>               intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
>               intel_encoder->pre_enable = vlv_hdmi_pre_enable;
>               intel_encoder->enable = vlv_enable_hdmi;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2107434a42e4..9baffae4f9f8 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7758,7 +7758,7 @@ void intel_init_pm(struct drm_device *dev)
>       } else if (IS_CHERRYVIEW(dev_priv)) {
>               vlv_setup_wm_latency(dev);
>               dev_priv->display.update_wm = vlv_update_wm;
> -     } else if (IS_VALLEYVIEW(dev)) {
> +     } else if (IS_VALLEYVIEW(dev_priv)) {
>               vlv_setup_wm_latency(dev);
>               dev_priv->display.update_wm = vlv_update_wm;
>       } else if (IS_PINEVIEW(dev)) {
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 3a6e1a93aed9..ee56a8756c07 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2589,7 +2589,6 @@ static void vlv_cmnlane_wa(struct drm_i915_private 
> *dev_priv)
>   */
>  void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
> resume)
>  {
> -     struct drm_device *dev = &dev_priv->drm;
>       struct i915_power_domains *power_domains = &dev_priv->power_domains;
>  
>       power_domains->initializing = true;
> @@ -2602,7 +2601,7 @@ void intel_power_domains_init_hw(struct 
> drm_i915_private *dev_priv, bool resume)
>               mutex_lock(&power_domains->lock);
>               chv_phy_control_init(dev_priv);
>               mutex_unlock(&power_domains->lock);
> -     } else if (IS_VALLEYVIEW(dev)) {
> +     } else if (IS_VALLEYVIEW(dev_priv)) {
>               mutex_lock(&power_domains->lock);
>               vlv_cmnlane_wa(dev_priv);
>               mutex_unlock(&power_domains->lock);
> -- 
> 2.7.4
> 
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