On Thu, Jan 12, 2017 at 09:17:06PM +0000, Chris Wilson wrote:
> On Mon, Jan 09, 2017 at 11:19:32AM +0000, Chris Wilson wrote:
> > On a non-llc system, the objects are created with .cache_level =
> > CACHE_NONE and so the transition to uncached for scanout is a no-op.
> > However, if the object was never written to, it will still be in the CPU
> > domain (having been zeroed out by shmemfs). Those cachelines need to be
> > flushed prior to display.
> > 
> > Reported-by: Vito Caputo
> > Fixes: a6a7cc4b7db6 ("drm/i915: Always flush the dirty CPU cache when 
> > pinning the scanout")
> > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
> > Cc: <drm-intel-fi...@lists.freedesktop.org> # v4.10-rc1+
> 
> Ping?

This patch fixes the problem for me, in case that's what the ping's for.

Out of curiosity the bug I reported described here be getting fixed in 4.10?
https://lists.freedesktop.org/archives/dri-devel/2017-January/128405.html

Thanks.

> 
> > ---
> >  drivers/gpu/drm/i915/i915_gem.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c 
> > b/drivers/gpu/drm/i915/i915_gem.c
> > index 76689b59fc90..bdb113ef8cfe 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -3514,7 +3514,7 @@ i915_gem_object_pin_to_display_plane(struct 
> > drm_i915_gem_object *obj,
> >     vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
> >  
> >     /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
> > -   if (obj->cache_dirty) {
> > +   if (obj->cache_dirty || obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
> >             i915_gem_clflush_object(obj, true);
> >             intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
> >     }
> > -- 
> > 2.11.0
> 
> -- 
> Chris Wilson, Intel Open Source Technology Centre
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