Op 10-08-17 om 18:20 schreef Chris Wilson:
> Another month, another story in the cache coherency saga. This time, we
> come to the realisation that i915_gem_object_is_coherent() has been
> reporting whether we can read from the target without requiring a cache
> invalidate; but we were using it in places for testing whether we could
> write into the object without requiring a cache flush. So split the
> tracking into two, one to decide before reads, one after writes.
> See commit e27ab73d17ef ("drm/i915: Mark CPU cache as dirty on every
> transition for CPU writes") for the previous step in this saga.
> Testcase: igt/kms_mmap_write_crc
> Testcase: igt/kms_pwrite_crc
> Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
> Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
> Cc: Dongwon Kim <dongwon....@intel.com>
> Cc: Matt Roper <matthew.d.ro...@intel.com>
> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101109
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101555

Tested-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
Acked-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com>

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