On Wed, 25 Oct 2017, abhay.ku...@intel.com wrote: > From: Abhay Kumar <abhay.ku...@intel.com> > > In glk when device boots with only 1366x768 panel, HDA codec doesn't comeup. > This result in no audio forever as cdclk is < 96Mhz. > This chagne will ensure CD clock to be twice of BCLK.
So this issue was never resolved was it? Summing up, I think the ideas for solution were in order of preference: 1) Tie higher cdclk requirement to audio component get/put power callbacks, and bump up cdclk when audio requests power 2) Bump up cdclk during i915 probe, after that require higher cdclk only when has_audio is true 3) Require higher cdclk whenever there are display outputs that are capable of hda 4) Always require higher cdclk (this patch) BR, Jani. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102937 > Signed-off-by: Abhay Kumar <abhay.ku...@intel.com> > --- > drivers/gpu/drm/i915/intel_cdclk.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c > b/drivers/gpu/drm/i915/intel_cdclk.c > index e8884c2ade98..185a70f0921c 100644 > --- a/drivers/gpu/drm/i915/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > @@ -1920,7 +1920,7 @@ int intel_crtc_compute_min_cdclk(const struct > intel_crtc_state *crtc_state) > /* According to BSpec, "The CD clock frequency must be at least twice > * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. > */ > - if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) > + if (INTEL_GEN(dev_priv) >= 9) > min_cdclk = max(2 * 96000, min_cdclk); > > if (min_cdclk > dev_priv->max_cdclk_freq) { -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
