On Mon, Mar 12, 2018 at 09:09:54PM -0700, Dhinakaran Pandiyan wrote:
> What was called SRD_DEBUG(0x6F860) on HSW and BDW was renamed to PSR_MASK
> SKL onwards, add a note next to the macro definition.
> There is also a different PSR_DEBUG on SKL+ to add to the confusion.
> 
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>

Acked-by: Rodrigo Vivi <rodrigo.v...@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 23c0f9bdf591..e8a4b61397ba 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4186,13 +4186,13 @@ enum {
>  #define EDP_PSR_PERF_CNT             _MMIO(dev_priv->psr_mmio_base + 0x44)
>  #define   EDP_PSR_PERF_CNT_MASK              0xffffff
>  
> -#define EDP_PSR_DEBUG                                
> _MMIO(dev_priv->psr_mmio_base + 0x60)
> +#define EDP_PSR_DEBUG                                
> _MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */
>  #define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1<<28)
>  #define   EDP_PSR_DEBUG_MASK_LPSP              (1<<27)
>  #define   EDP_PSR_DEBUG_MASK_MEMUP             (1<<26)
>  #define   EDP_PSR_DEBUG_MASK_HPD               (1<<25)
>  #define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1<<16)
> -#define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15)
> +#define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15) /* SKL+ */
>  
>  #define EDP_PSR2_CTL                 _MMIO(0x6f900)
>  #define   EDP_PSR2_ENABLE            (1<<31)
> -- 
> 2.14.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Reply via email to