On Thu, 05 Apr 2018, Mahesh Kumar <mahesh1.ku...@intel.com> wrote:
> This patch adds support to start tracking status of DBUF slices.
> This is foundation to introduce support for enabling/disabling second
> DBUF slice dynamically for ICL.
>
> Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com>
> Reviewed-by: James Ausmus <james.aus...@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h         |  1 +
>  drivers/gpu/drm/i915/intel_display.c    |  5 +++++
>  drivers/gpu/drm/i915/intel_pm.c         | 20 ++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_runtime_pm.c |  4 ++++
>  4 files changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5373b171bb96..e51da42297d8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1184,6 +1184,7 @@ static inline bool skl_ddb_entry_equal(const struct 
> skl_ddb_entry *e1,
>  struct skl_ddb_allocation {
>       struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* 
> packed/uv */
>       struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
> +     uint8_t enabled_slices; /* GEN11 has configurable 2 slices */

Please prefer kernel types u8/u16/u32/u64 over uint8_t and friends. It's
fine to use the stdint types when the context uses them, but please
let's not add new ones.

BR,
Jani.


>  };
>  
>  struct skl_wm_values {
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 415fb8cf2cf4..96a1e6a7f69e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11385,6 +11385,11 @@ static void verify_wm_state(struct drm_crtc *crtc,
>       skl_ddb_get_hw_state(dev_priv, &hw_ddb);
>       sw_ddb = &dev_priv->wm.skl_hw.ddb;
>  
> +     if (INTEL_GEN(dev_priv) >= 11)
> +             if (hw_ddb.enabled_slices != sw_ddb->enabled_slices)
> +                     DRM_ERROR("mismatch in DBUF Slices (expected %u, got 
> %u)\n",
> +                               sw_ddb->enabled_slices,
> +                               hw_ddb.enabled_slices);
>       /* planes */
>       for_each_universal_plane(dev_priv, pipe, plane) {
>               hw_plane_wm = &hw_wm.planes[plane];
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 19e82aaa9863..3ff37d5ba353 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3567,6 +3567,23 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
>       return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
>  }
>  
> +static uint8_t intel_enabled_dbuf_slices_num(struct drm_i915_private 
> *dev_priv)
> +{
> +     uint8_t enabled_slices;
> +
> +     /* Slice 1 will always be enabled */
> +     enabled_slices = 1;
> +
> +     /* Gen prior to GEN11 have only one DBuf slice */
> +     if (INTEL_GEN(dev_priv) < 11)
> +             return enabled_slices;
> +
> +     if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
> +             enabled_slices++;
> +
> +     return enabled_slices;
> +}
> +
>  /*
>   * FIXME: We still don't have the proper code detect if we need to apply the 
> WA,
>   * so assume we'll always need it in order to avoid underruns.
> @@ -3832,6 +3849,8 @@ void skl_ddb_get_hw_state(struct drm_i915_private 
> *dev_priv,
>  
>       memset(ddb, 0, sizeof(*ddb));
>  
> +     ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
> +
>       for_each_intel_crtc(&dev_priv->drm, crtc) {
>               enum intel_display_power_domain power_domain;
>               enum plane_id plane_id;
> @@ -5050,6 +5069,7 @@ skl_copy_wm_for_pipe(struct skl_wm_values *dst,
>              sizeof(dst->ddb.y_plane[pipe]));
>       memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
>              sizeof(dst->ddb.plane[pipe]));
> +     dst->ddb.enabled_slices = src->ddb.enabled_slices;
>  }
>  
>  static void
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 53ea564f971e..58be542d660b 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2664,6 +2664,8 @@ static void icl_dbuf_enable(struct drm_i915_private 
> *dev_priv)
>       if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
>           !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
>               DRM_ERROR("DBuf power enable timeout\n");
> +     else
> +             dev_priv->wm.skl_hw.ddb.enabled_slices = 2;
>  }
>  
>  static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
> @@ -2677,6 +2679,8 @@ static void icl_dbuf_disable(struct drm_i915_private 
> *dev_priv)
>       if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
>           (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
>               DRM_ERROR("DBuf power disable timeout!\n");
> +     else
> +             dev_priv->wm.skl_hw.ddb.enabled_slices = 0;
>  }
>  
>  static void icl_mbus_init(struct drm_i915_private *dev_priv)

-- 
Jani Nikula, Intel Open Source Technology Center
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