Hi Lionel, Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on v4.17 next-20180605] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Lionel-Landwerlin/drm-i915-perf-allow-holding-preemption-on-filtered-ctx/20180607-005605 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: x86_64-randconfig-x011-201822 (attached as .config) compiler: gcc-7 (Debian 7.3.0-16) 7.3.0 reproduce: # save the attached .config to linux build tree make ARCH=x86_64 All errors (new ones prefixed by >>): drivers/gpu//drm/i915/intel_lrc.c: In function 'gen8_emit_bb_start': >> drivers/gpu//drm/i915/intel_lrc.c:1981:6: error: 'struct i915_request' has >> no member named 'gem_context' (rq->gem_context->perf_disabled_preemption ? ^~ vim +1981 drivers/gpu//drm/i915/intel_lrc.c 1934 1935 static int gen8_emit_bb_start(struct i915_request *rq, 1936 u64 offset, u32 len, 1937 const unsigned int flags) 1938 { 1939 u32 *cs; 1940 int ret; 1941 1942 /* Don't rely in hw updating PDPs, specially in lite-restore. 1943 * Ideally, we should set Force PD Restore in ctx descriptor, 1944 * but we can't. Force Restore would be a second option, but 1945 * it is unsafe in case of lite-restore (because the ctx is 1946 * not idle). PML4 is allocated during ppgtt init so this is 1947 * not needed in 48-bit.*/ 1948 if (rq->ctx->ppgtt && 1949 (intel_engine_flag(rq->engine) & rq->ctx->ppgtt->pd_dirty_rings) && 1950 !i915_vm_is_48bit(&rq->ctx->ppgtt->base) && 1951 !intel_vgpu_active(rq->i915)) { 1952 ret = intel_logical_ring_emit_pdps(rq); 1953 if (ret) 1954 return ret; 1955 1956 rq->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(rq->engine); 1957 } 1958 1959 cs = intel_ring_begin(rq, 6); 1960 if (IS_ERR(cs)) 1961 return PTR_ERR(cs); 1962 1963 /* 1964 * WaDisableCtxRestoreArbitration:bdw,chv 1965 * 1966 * We don't need to perform MI_ARB_ENABLE as often as we do (in 1967 * particular all the gen that do not need the w/a at all!), if we 1968 * took care to make sure that on every switch into this context 1969 * (both ordinary and for preemption) that arbitrartion was enabled 1970 * we would be fine. However, there doesn't seem to be a downside to 1971 * being paranoid and making sure it is set before each batch and 1972 * every context-switch. 1973 * 1974 * Note that if we fail to enable arbitration before the request 1975 * is complete, then we do not see the context-switch interrupt and 1976 * the engine hangs (with RING_HEAD == RING_TAIL). 1977 * 1978 * That satisfies both the GPGPU w/a and our heavy-handed paranoia. 1979 */ 1980 *cs++ = MI_ARB_ON_OFF | > 1981 (rq->gem_context->perf_disabled_preemption ? 1982 MI_ARB_DISABLE : MI_ARB_ENABLE); 1983 1984 /* FIXME(BDW): Address space and security selectors. */ 1985 *cs++ = MI_BATCH_BUFFER_START_GEN8 | 1986 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) | 1987 (flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0); 1988 *cs++ = lower_32_bits(offset); 1989 *cs++ = upper_32_bits(offset); 1990 1991 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 1992 *cs++ = MI_NOOP; 1993 intel_ring_advance(rq, cs); 1994 1995 return 0; 1996 } 1997 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
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