Chris Wilson <ch...@chris-wilson.co.uk> writes:

> BIT(14) is not sticking in 0xe4f4 so we have no idea if the w/a is still

Now we have some idea. It was in mcr range register thus verification
was doomed to fail. Fix in list.

-Mika

> in effect when it needs to be. Until that is resolved, remove the
> failing bit.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/1169
> Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 ---
>  1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 62b43f538a56..4bbea781c142 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -598,9 +598,6 @@ static void tgl_ctx_workarounds_init(struct 
> intel_engine_cs *engine,
>       wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
>              IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
>                           FF_MODE2_TDS_TIMER_MASK);
> -
> -     /* Wa_1606931601:tgl */
> -     WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
>  }
>  
>  static void
> -- 
> 2.25.0
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